NLSC16 / CSC-16 My instruction set.

[Nickster258]

This looks nice, im glad to see you're moving away from the microcoded style ISAs which directly interact with hardware.

I have a few gripes about it but meh, thats me the person who likes x86.

Thanks! I spent a long time just thinking about it and slowly making adjustments. I want my next CPU to be well planned out and have great functionality with good speed.

Is the fact that it will take 2 cycles to branch all that bad? I notice many use that and I can add 13 more branch functions if I wanted to, but it may not be worth it. (Plus others can add their own branch functions and have it somewhat customizable.)

Do you mean in terms of a branch delay slot? for example:

BEQ, R1, R5, 0x5
NOP

Or a compare before a branch:

CMP, R1, R5
BEQ, 0x5

MIPS uses the first way while x86 and ARM use the second. While they are not recommended if you can avoid them but if it allows you to add 13 more branches then go for it. Kind of a necessary evil

Either one actually. I am debating on making both of those plausible since I have so much room in the branch function.