01-09-2014, 07:51 PM
(This post was last modified: 01-09-2014, 09:22 PM by Cutlassw30.)
(01-09-2014, 04:42 PM)redstonewarrior Wrote: I moderately hate you. On a side note, you can get more CISC with this, and at one point, get to do some logically interesting things in the instruction decoding sections, including register renaming, memory fetch optimization, instruction reordering, and more. You'll need about 2 ORE builds worth of space for this. 256 may not be high enough for the overlapping busses.
Just kidding. It would be under a plot, but still monstrous and unusable. The instruction decoding logic would literally be the slowest part.
CISC sucks.
This is more RISC than ARM is...