07-09-2015, 10:56 PM
(This post was last modified: 07-10-2015, 03:09 AM by CrazyGuy108.)
This thread will document the adders and ALUs I have designed using Logisim. You can find the ORable XOR Gate (Required for all my ALUs) here
Completed:
8bit KSA ALU
8bit CLE ALU
In Progress:
None.
I will take requests with bit sizes no more than 8. I may do 16, though. Specifics, like OR for carry propagation or anything else like that I can do as well.
Completed:
8bit KSA ALU
8bit CLE ALU
In Progress:
None.
I will take requests with bit sizes no more than 8. I may do 16, though. Specifics, like OR for carry propagation or anything else like that I can do as well.