ERIS v2.0 CPU

[gera279]

This thread showcases my WIP CPU. It will be updated as I make major advancements in the construction of it.

Hey all,
I've begun work on a new CPU, after my last CPU was abandoned along with the old O.R.E. server. It is entirely solid state, and utilises my own IS, entitled ERIS v2.0 (Extended Redstone Instruction Set). I'll be putting up a link to a thread with the IS in shortly.

Specs:
8 bit ALU
3 bit reg addr.
5 bit RAM addr. (planned)
5 bit PROM (planned)
4 flags - uncondis, if 0, if cout, if underflow
7 tick ALU
11 tick dataloop
Currently unpipelined, though due to be at some point

Pics:
Overview of the entire CPU (latest pic)


ALU, regs and decoders


BCD converter and screen decoders

I/O with computer shut down…


…and turned on.


Thanks for viewing!

Any feedback is appreciated.

[tokumei]

I've never seen so much work put into the user interface... Needless to say, it looks pretty sweet

[gera279]

Thanks xD I forgot to mention that the user interface was designed by GG, so credit to him for that.

[Magic :^)]

but wait I thought that was me!
I even put in the stupid knight rider thing D:


#magicRekt

[LordDecapo]

Sweet
I hope this gets pipeline, would be awesome to see a 11tick CPU

[jxu]

cool
maybe I should get back

[gera279]

Was that you Magic?! Sorry, I can't really remember to be honest… What "knight rider" thing?

[Magic :^)]

Was that you Magic?! Sorry, I can't really remember to be honest… What "knight rider" thing?

http://www.youtube.com/watch?v=Mo8Qls0HnWo
A bit late now, but that light thing ^

it was a good idea at the time... xD