New CPU!

[Iceglade]

I am back redstoning, and am now working on an all-new CPU using a modified RISC-16 set. I won't post updates or any of that, however the IS is completed, and I guess I'll post this here because some people wanted to see it. It's nothing more than a RISC-16 based, 3 bit opcode IS with "custom" functionality in place of JALR.

You can see better for yourself:



The only difference involves some slight modifications to argument structures and the IO command in place of JALR. For an unconditional jump one can simply branch if eual a register with itself.

Peace! -Ice

[greatgamer34]

use a 2 operand system instead of a 3 operand, it can get you room for 2 more imm and another opcode bit

[Dcentrics]

ICE NO we no like this. I clean up and lock thread ok. good. i ar vensuala n i cleahn up threads lik dis

[Iceglade]

no

[Dcentrics]

D:< BUT IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIICCCCCCCCCCCCCCCCCCCCCCCCEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEE

[Dcentrics]

its a bit like BUT MUUUUUUUUUUUUUUUUUUUUUUM

[Cutlassw30]

dude just use memory mapped I/O. JALR is so much more important

[Spidermy9]

ERHMAGERHD ITS CUT

[redstonewarrior]

CUUUUUUUUUUUUUUUUUUHHHHHHHHHHHHHHHHHHHHHHHHTTTTTTTT

[greatgamer34]

Oh wow, he still loves us!