my first Computer progress

[ImaCreeperKaBoom]

I have started my first CPU based on what I understand about them. I'm using my ICA ALU.

ALU specifics:
4 tick add/subtract
multiple once I get my xbox back out anyway
Logic:
AND/AND
OR/NOR
XOR/XNOR
NOT



flags are grabbed off the ALU
ZERO flag: is triggered if zero is the result of the ALU  (first on the right)
PARITY FLAG (odd):is triggered if the first bit is one and the result of the ALU is not zero (second on the right)
PARITY FLAG (even): is triggered if the first bit is zero and the result of the ALU is not zero (third on the right)
(I noticed that all odd binary numbers first bit is one, and all even numbers are zero)
OVERFLOW FLAG: is triggered if the number is greater than 8 bits either as 257 or -1 (third is 257 and fourth is -1)


the last two trigger when the shift registers are zero





next I added registers (purple) and shift registers (red)
the AX register holds the value the ALU is currently using
the shift register is used to shift the value left or right (I use these for multiplication)



next I added a caching system L1 (brown and grey) L2 (lime)

L1 cache is split up into two sets set one (grey) set two (brown)
the L1 cache is used to hold values that are going to be used or used often I.E. if your doing 5x+2=y the 5 and 2 would be stored here. set 1 is used for the set A shift and AX registers, set 2 is used for the set B shift and AX registers
both sets are saved at the same time I.E. if you want to save 2 you it will be saved to both sets if desired but it can be saved to just one set. I.E. if 2 is send over it can be saved to set 1 cell 2 and set 2 cell 3 (or any combination of the cells.)  each set is read individually I.E. set 1 cell 2 has 5 that is sent straight to the registers therefor both register sets can be saved at the same time.

L2 cache is used if the value is being used again immediately by the ALU, I.E. if your doing a count up by a number like 2+x then the two can be stored here this cell is much faster at both writing and reading and can be sent to either register sets. since this number is either constant like 2+x or is a value the ALU is going to use again it frees up the cache as this number will only be used by one register set therefor keeping an even bit number in the cache.

 next I added an I/O
green output takes the ALU result and sends it to RAM or other areas
pink input takes values from RAM or other areas


this is version 1.1 I'm going to rebuild it once more as I saw something I could do to make it a bit more neat and will be coloring is as it is in the previous pictures.


I'm almost done with the control unit which will be EEPROM. I'm doing it like that because I hate using torches to program so instead there will be a lever system where you select the program line and hit levers once your done with the line hit save and move on. this will also allow you to save programs to a HDD and load/save programs from there.

the HDD will hold both the program and its information I.E. if your doing 2+x and you want to stop it it will put any information that is saved in cache, RAM and when you load it back up it will put everything back which will also allow for deletion of the data. I'm not sure yet but hopefully it will be fast enough that you can load up more lines for the HDD I.E. if your program is 40 lines long and the EEPROM is 32 (which it will be) it can call for the next lines.

The RAM will be quad channel and both read/writable at the same time for m different parts of the computer. I.E. channel one can be written by the CPU cache while the display reads from it. such as channel 1 cell 5 is read by display while cell 3 is written by CPU. since its 4 channel: all of this can happen during the same clock cycle allowing large amounts of data to be moved at once
C1: CPU read cell 2     GPU  write cell 6
C2: CPU write cell 12   HDD write cell 3
C3: HDD read cell 1     GPU  write cell 9
C4: BCD read cell 8      CPU  write cell 10 
so far it takes 1.2 seconds to gather the data from the decode input to the data leaving or entering the RAM. but that is if all is at once 32 bits can be accessed and 32 stored per 1.2 seconds so not that bad really. but a multiple channels cant be accessed by anyone area at the same time I.E. CPU cant read from C1 and C2 during a clock cycle at least not yet I'm working on that.

GPU
the GPU will be responsible for taking the CPU data and turning it into a picture whether its a graph, symbol, polygon, or letter. then being able to rotate, scale, or translate the images. I plan on using vector graphing in which each core is responsible for a vector. therefor the more cores the more and faster the images can change.
CPU
the CPU is responsible for the user input and turning it into a value used by the GPU.
RAM
The RAM will hold any and all values that are needed to run the program
CU
the CU is responsible for controlling the computer. it will instruct the computer on what to do it will be taking inputs for branching.
RAM
the RAM is going to hold any values the are necessary to run the program
HDD
will be used to save and load programs and data values in to the computer. 


this is the interactions:
the user will select a program in this case the program is a game in witch the user uses a d pad to move a box around and collect coins. this is what my first major program will be once I get all the bugs out.
the HDD signals to the CU that the program is incoming. the EEPROM will load the program. the HDD sends a signal saying the program is done loading. the EEPROM will start the program by having the GPU access the RAM for the start menu. also having the CPU access the RAM for the values it needs. once the menu is loaded the player will hit the d pad this sends a signal the CPU it takes the value and does math to a number.to explain this: if the user goes over one pixel the CPU will add that number to the value of the location of the last position 1+x so if the last position of the pixel was 2, 3 it will add 1 + 2 1+3 then send 3, 4 to the GPU which will determine by the program if its a translation, rotation ,or scale. in this case its a translation so it finds all the pixels that are related to that coordinate and add 1 to them all. if the program calls that the area affecting needs to be filled it will refill as the new pixels render. basically the CPU keeps track of where the user is and the GPU re-renders the affected pixels. therefor the location of the player will be stored in L1 cache if the program is mostly just translation like this game will be then the value of one move will be stored in L2 as this will be used to add to the old location E.I. L1 has a 5 and L1 has 1 when the player makes a move it will just grab the one from L2 and the 5 from L1 and add them. so now the player hits an enter key the CPU will nothing to it and address it straight to the GPU and RAM where it will load up the game. this is done by the HDD it will load into the GPU cache the start points of the box and coins and the location of the player pixel to the CPU. then the un rendered areas are stored in RAM. when the player moves in a direction the box moves one pixel per selection the above process is done to the nes value and the box is rendered into its new location. once a coin comes into the boxes range the coin will disappear the GPU is responsible for knowing where the coins are and when to collect them. once a coin is gather the GPU sends the data the the CPU which then adds it the the score and stores it in RAM and sends it to the BCD. as the player moves up the GPU will gather new render data from the RAM for the new area. once the level is over you can save and continue later from that point or continue.

this is a general idea of what I'm working on I know it will be slow as hell but as long as the games don't need a fast reaction like space invaders or something it doesn't really matter. all your doing is moving a box around gathering coins, speed of the player is un important. and yes I know that I could just build a dedicated system to move a box around but guess what there will be other games and programs and that is the point.

any suggests or ideas, or help would be awesome if anyone want to help me actually build it let me know ill build it on the server with you if its allowed. I don't know if it does run if it would crash the server as it is a large project but I'm sure my computer can handle it. so I will build it on mine I'm just asking ahead of time before I actually start it. right now I'm just working on all the components and getting them as small and fast as possible.

things I do need are division there are no tutorials on youtube save for newomasters which I cant for the life of me make 8 bit I would like to use his design as it is very fast. I also need someone to teach me about pipelining and pipeline syncing, as well as how to build a CPU unless what I describe my CPU as is what that is. thanks for staying with this and have a good day.

[ddthj]

A rather ambitious project for your first CPU....

I like it

[ImaCreeperKaBoom]

update on my CPU thingy:
I finally finished the design of the main part of the CPU. I added a few things, cleaned up the overall look and made it a bit smaller and faster. the final specs are:
ALU white logic black
ICA with AND, NAND, OR, NOR, XOR, XNOR, NOT flags grey zero, even parity, odd parity, overflow, shift registers zero
add/subtract and multiplication by addition
5 ticks result of either addition or subtraction
3 ticks logic triggered 2 ticks before ALU result
7 ticks flag trigger its slower because the result is needed for the flags to be triggered

Cache L1: set one brown set two light grey
duel read quasi duel write 48 bits
3 ticks write. 3 ticks to save to result after it leaves the ALU
3 ticks read. 3 ticks to reach shift register read mux. therefor 6 ticks to read and send

Cache L2: lime
2 ticks write
1 tick read
1 tick to reach register write 2 ticks from read to write

shift registers red
2 ticks write
2 ticks shift
0 ticks to AX register

AX register: Purple
2 ticks write
0 ticks read

1.5 seconds for complete loop at the slowest going through L1
1.1 seconds for complete loop at the fastest going through L2
therefor the longest multiplication is shift register's last bit is active sine L2 is used for multiplication 1.1x8 is 8.8 seconds for the longest result. I plan on having a dedicated multiplier input so it can do the equation faster than waiting for the CU to read the next line since the clock is going to be at least 3 seconds probably. since it only takes 1.1 seconds to give a result no since waiting 24 seconds for the CU to do all the instructions if that makes since Smile  

external ALU output: green
2 ticks form result
external ALU input: pink
3 ticks to be written in cache

I added an external output for each cache 5 ticks to leave the output mux orange bus lines
I stream lined the design its flat on top and bottom and looks very organized and neat Smile

over all size 27x54x22  32076 blocks cubed

[ImaCreeperKaBoom]

new update: RAM is done
quad channel each channel can be read and written at the same time and by different part of the computer I.E.
Channel 1: can be read by the CPU while being written by the GPU
Channel 2: can be read by the display (BCD) and written by the HDD
Channel 3: can be read by the GPU and written by the CPU
channel 4: can be read by the HDD and written by the CPU
all the above can happen during the same clock cycle

the read time which includes decoding RAM address and bussing it to the output is 25 ticks or 2.5 seconds therefor 12.5 bits can be read per every second
the write time is 15 ticks or 1.5 seconds which includes decoding RAM address and bussing the value to the address therefor 21.333 bits can be written per every second

there is a hard code for which channel to use so its not slowed down by a decoder
address goes as:
first four bits are the address and the last bit is whether its reading or writing to the address
00000
decoder red
address switch magenta glass
RAM light blue
data in/output the multi color glass area
each color goes with a different part of the computer yellow, blue, lime, white