HCP V3 - Brief History And Progress

[Halflife390]

Prepare to witness a CPU like no other



I present to you the:



 
Hello fellow redstoners!

As some of you don’t know iv actually been a member of ORE for a long time, nearly 2 years. I have taken a year’s break from the server as I had a lot of IRL things to take care of. However when I was on the server a year ago I worked on a large project called the HCP V2 (Details here https://forum.openredstone.org/showthrea...ght=hcp+v2). The HCP V2 (Half.corp Computing Platform Version 2) is a large fully Von Neumann CPU I built. The idea came to me when I read a really interesting book and watched a really interesting video that described an entire CPU in terms of logic gates. Therefore the entire design in the book could literally be copies into MC, which is what I did. The transition from diagram to redstone was not without its problems however. Firstly it required a large 2 way bus which was possible but very slow. However I did finish the CPU and it can be found on my old plot if you wish to see it. I never finished debugging it or added all the bells and whistles I said I would. Even though it has a 60 tick clock and takes up my entire plot I’m proud of it as it proves that the idea and concept works.

Someone said something while I was building it that got me thinking:

I was explaining to someone that my Von Neumann architecture was better than Harvard as my CPU can move any value or instruction from any memory space such as GPR or RAM to any other memory location inside the computer in 1 instruction thanks to the 2 way combined address and data bus. However, the guy said that even though his CPU would require several instructions to do that, his Harvard architecture was simpler and so his clock was faster allowing him to accomplish it faster than my 1 instruction Von Neumann.
That made me think that after I finish the HCP V2 I would make the HCP V3. It would be a reincarnation of my Von Neumann machine but it would be modified Harvard. It would be the next generation of the design in the book. And here we are over a year later…
 
The HCP V3 is not built, its not even started. Before I even think about starting it I have decided to prototype it first. I am currently in the process of making several prototypes of the HCP that will allow me to see which idea works, how things will be done and to adjust the architecture for speed. That’s right folks, the HCP V2 focused on functionality where as this one focuses more on speed.
This is where I hit the first problem. I wanted to have a really versatile machine that was capable of many functions but did them at great speed. No architecture I knew could offer this, so I invented my own.

Rapid-Core Architecture

The Rapid-Core arch allows for speed and functionality as I have custom designed it in such a way. The arch brings together the idea of Von Neumann and Harvard to make a hybrid (modified Harvard). The arch is still in its infancy and will require more development before full implementation. If others wish to use this arch I will post about the specifics of it on another thread, it’s quite different to most archs out there.

Current Progress


Currently I am prototyping different parts of the HCP V3, I have made 2 full scale CPU prototypes, the HCP P1 and the HCP P2. Prototyping is a really useful tool as I have learned so much from it. Originally the secret to speed was going to be instant repeaters, bad idea as I have now discovered. I have just finished the HCP P2 and it is quite promising. It is still very different to the final product as each prototype will encompass a new feature of the HCP V3 such as caching and pipelineing. Some features are being debated, some have been removed through prototyping, some are in the pipeline (PUN CERTAINLY INTENDED!)

So here are the specs of the second prototype:

• HCP V3 P2 (Half.corp Computing Platform Version 3 Prototype 2)
  
• Rapid-Core Modified Harvard Architecture (My own design =)
  
• Running the Redset V4 ISA
  
• 8 Bit data, 16 bit instructions
  
• 6 tick CLE ALU by Embizone (God of ALU's)
  
• ALU can perform ADD, SUB, NOT, OR, AND, XOR (No negative support)
  
• 32 bytes of RAM made up of 16 2 byte addresses for instructions
  
• Only unconditional branching
  
• Loosely based on the Von Neumann design in the book
  
• DEEP RISC ISA (DEEP = Fixed operands for maximum versatility)
  
• 16 bit instruction words
  
• 8x 1 byte GPR
  
• Currently running a clock speed of 22 ticks. Note that the CPU can run faster but I have not bothered speeding it up for time sake
  
• Is small, compact and fast
  
• Is running an ISA that is designed to have a few more features such as general indicators but have not been added for time sake (Its only a prototype)
  

Here is the FULL instruction set that it is only half running:



 
 Finally some nice pictures to break up this wall of text:































Here is an image of the first prototype the HCP V3 P1 with all its gloriously crap instant repeaters






The prototype is great, its show my arch is certainly possible and it works. I have programmed some basic adding programs and the Fibonacci sequence all with success (after lots of tweaking and debugging)

The HCP V3


The HCP V3's spec will be different from that of the prototypes. Here is an idea of what it might look like as it is always changing:

• HCP V3 (Half.corp Computing Platform Version 3)
  
• Rapid-Core Modified Harvard Architecture (My own design =)
  
• Running the Redset V5 ISA
  
• 8 Bit data, 16 bit instructions
  
• 6 tick CLE ALU by Embizone (God of ALU's)
  
• ALU can perform ADD, SUB, NOT, OR, AND, XOR, CMP
  
• 512 bytes of RAM made up of 256 2 byte addresses for instructions
  
• Conditional and unconditional branching dictated by 6 FLAGS (A=B, A<B, A>B, A=0, Overflow, Negative)
  
• Loosely based on the Von Neumann design in the book
  
• RISC ISA
  
• 16 bit instruction words
  
• 8x 1 byte GPR
  
• Clock speed of 10-15 ticks (THIS IS NOT GUARANTEED, it may well be longer but will still be reasonable)
  
• Is small, compact and fast
  
• Will have a full caching system composed of a RAM input and output cache of unknown sizes
  
• Will have a Memory Control to control caching and manage cache misses
  
• 4 stage instruction pipeline (It has moved from 3 to 4 so it could move again)
  
• Stack system of unknown size
  
• PMU - Pipeline Management Unit (Does what it says on the tin)
  
• Will have a full I/O bus supporting 256 different I/O devices
  
• Could support interrupts but have not decided yet
  
• Full control room with debugger and programming aids
  
• More specs will be added later
  

As you can see there is still lots to prototype and test such as pipelining and caching. This is why the final HCP V3 will not be seen until at least 6 months. This is a big project and will take my time each step of the way. If other wish to help me on this endeavor then I will consider it.

Whats Next


I would love to sit here and say that tomorrow I will do this and next week I will do that but unfortunately I cant. This is because I will be taking another break from the server starting from today. This break will not be as long, only about 2 months and most likely I will still visit the server every week just to check in with the latest banta, shenanigans and tomfoolery we commonly get up to. I am taking this break as I have lots of postponed and exciting IRL project that I need to divert my attention too. One of them is MC related and very exciting, there might be a post soon offering parts in it if other wish to help me with it. But rest assured, after these are complete I will return to finish what I have started.

Thankyou for reading and I am sorry for this huge wall of text! Please watch out for updates and for the exciting projects that you guys might be able to get involved in!

[dylanrusell]

The command Jump if negative seems rather redundant since you could do jump if less than and compare $0 to the register in question. Since $0 is always a constant 0 why not just check if the number is less than and it will always tell you if it's negative number.

Also you keep mentioning a book, yet you are not citing it. My question is what book are you referring to?

[VoltzLive]

There's a lot more than Jump if negative wrong with your ISA.


There's so much redundancy in your op code you could handle with a 4-bit and a third operand.
You can compress:
    branching into a single command with an operand as the branch predicate.
    Indicator lights into a single command with an operand as which light
    Stack into a single command with a flag bit, push/pop
    And you can compress all of your Boolean maths into a single op

[Halflife390]

The command Jump if negative seems rather redundant since you could do jump if less than and compare $0 to the register in question. Since $0 is always a constant 0 why not just check if the number is less than and it will always tell you if it's negative number.

Also you keep mentioning a book, yet you are not citing it. My question is what book are you referring to?

But that wont work as my CPU can not handle negative numbers, so when comparing it with zero the answer will always be greater than. The only reason I would have this flag is for something like a calculator program that would check the result of a subtraction calculation to see if the overflow bit is off. This would then send an error saying that the answer is negative.

Also the book is called But How Do It Know by J. Clark Scott

[Halflife390]

There's a lot more than Jump if negative wrong with your ISA.


There's so much redundancy in your op code you could handle with a 4-bit and a third operand.
You can compress:
    branching into a single command with an operand as the branch predicate.
    Indicator lights into a single command with an operand as which light
    Stack into a single command with a flag bit, push/pop
    And you can compress all of your Boolean maths into a single op

I completely agree. By trying to make the CPU have as much freedom as possible (the programmer can control any part of the CPU at any time using instructions) I have used what I call a deep RISC ISA. This means that the operands are fixed and cannot be changed. No matter what opcode you are using, you will always be able to read and write to and from registers as they are fixed in. On the plus side you have more control. On the down side it leads to bigger word lengths and as you point out above, multiple codes for 1 command. The HCP V3 will not used deep RISC, more functionality beats the freedom in this case.

[Halflife390]

  Only two comments!?!?  I must of left everyone speechless! 

[LordDecapo]

What do you plan to have in your caches? Like just instructions? Just data? Both ?

[Halflife390]

What do you plan to have in your caches? Like just instructions? Just data? Both ?

RAM will store both instructions and data and so will the caches. BTW, whats with the Spirited Away profile pic?

[Magic :^)]

BTW, whats with the Spirited Away profile pic?

funny how the staff are getting anime avatars innit, first tuchi with ichigo and now capo with that thing from spirited away... Maybe I should change my avatar too xD

[Halflife390]

Anime is slowly consuming us XD

[Magic :^)]

Heh ive been consumed looong ago. I have become one with the ether

[LordDecapo]

I have had that avatar made for ages, I finally got with Tyler so he could raise the file size limit and allow me to upload it xD.
Cache(s?) You will have multiple?
What kinda replacement algorithm are you gonna use?

[Halflife390]

Input and Output cache. But considering that you wont be writing to RAM that often this might be omitted and a simpler system will be put in place to do this. I'm not using any algorithm at the moment, when the cache is full it will cease accessing RAM until it reaches the last memory location or a cache miss occurs. The it will be purged and new data will replace it. Obviously this isn't very efficient but as I have never done caching before in redstone I'm starting off simple.