Ninja Stacker CPU

[tokumei]

Related Links:
NJIS-8S Instruction Set
Transputer Architecture

I've decided to challenge myself by doing something I've never done before. I've made a couple other PUs and CPUs in my time on ORE/RDF, but I've never before messed with a stack architecture. So, my next project will be the Ninja Stacker, NJSTK for short. It's an 8-bit stack-based processor based on my new NJIS-8S instruction set and influenced by the Transputer architecture. I'm essentially making a Transputer without workspaces and processes.

Features:

• 1 Hz clock cycle
  
• 4 stage pipeline (fetch-fetch-decode-execute)
  
• 64 stack registers
  
• 64 lines of PROM
  

Feedback pl0x :)

[tokumei]

I can has feedback???

[LordDecapo]

Very nice

Btw, a 1hz fetch stage with 256 lines is HARD AS BAWLS.
cause u have to incriment the PC, send that to PROM decoders then load that value into ur decoders. My 6 tick clock has that in 3 stages (the actual processing only takes 3 cycles)
Just wanted to try and give a heads up..
I had 10 tick clock and 128 lines (shit decoder then) and it took 2 stages (PC incriment + lookup)


also I REALLY hope you make this  .
I wanna see how fast and functional it can be

When will u be starting the actual build?

[tokumei]

Technically, the instruction pointer increment is the same as the execute stage, because there are some instructions which alter the instruction pointer. You're still right, I'm cutting it close with 256 instructions, but I've calculated it and I should be able to fetch every second. If push comes to shove, I'll lower it to 64 instructions.

I do not have school next week. I'll probably do a lot more concept work and initial design then, and I'll do some actual experimenting with the clock speed.

I won't start any "production" building until we upgrade to 1.8 in April.

[tokumei]

After some experimentation, I've found that it will take more than 10t to fetch instructions from a 256 byte ROM. Instead of downscaling the ROM size like I previously mentioned, I will instead allocate 2 stages for instruction fetching.

[LordDecapo]

+1 ^^

[tokumei]

These past few weeks have been busy, and I haven't had time to do much other than some chatbot programming in my spare time. I hope to continue work on this, then take a break for finals at school, then hopefully I can finish it during the summer.

[tokumei]

Update: I've updated the 8S instruction set to better reflect the Transputer architecture. Along with that, I've downscaled the memory sizes a bit; however, the instruction set still has the same extensive address capability.

[LordDecapo]

Sweet!