IizRCPUx8,,, NEARING COMPLETION!

[LordDecapo]

This weekend I was going to work on my Arch. Comparison writeup, but got the urge and will to get back to work on my CPU.
So Dylan and I got branch timing all good this weekend, as well as began serial RAM install. The RAM will use data prefetching to get Loads to the Registers fast enough.
So as it stands now, the specs are as follows:
-8bit data
-16-48 bit ( variable length ) custom CISC ISA
-7 stage pipeline
-10 tick Clock
-data Forwarding (to keep clock low)
-Fully conditional branching with support for Calls and Returns
-32 Bytes of RAM, with 32 additional addresses for Memory Mapping IO/hardware, and full support for expansiom up to 16bit RAM/hardware addressing
-128 lines of PROM, with support for an additional 128 (256 total) lines of program memor with current PC, 16bit Program Addressing, is usable with the addition of a Offset system.
-Inturrupt support, both internal/program induced as well as externaly induced.
-plus some extra stuff I probably forgot to put in this list, all features will be covered in a video overview I will make when it's done.



Note: Dylan Russel and I are doing a lot of work on this together, and I couldn't have implimented NY ISA nearly as well if I didn't have his help compacting, bussing, building, and designing hardware.

[greatgamer34]

Note: Dylan Russel and I are doing a lot of work on this together, and I couldn't have implimented NY ISA nearly as well if I didn't have his help compacting, bussing, building, and designing hardware.

i live in NY

[LordDecapo]

Thanks for the nazism bro lol

[CreepyTacoMan]

-32 Bytes of RAM, with 32 additional addresses for Memory Mapping IO/hardware, and full support for expansiom up to 16bit RAM/hardware addressing

does this mean software clue that you've been telling me would be so easy? ^_^

[LordDecapo]

yes lol i wanted to hook up a board to it, with ur help, since u made clue in the walls of Capo! lol xD ill add ur thingy to my thingy!

[LordDecapo]

UPDATE: so guys, Ntwede pointed out an issue relating to pipelining and my Call/Return functions, where the address stored to the stack when u preform a Call, would be about 2-3 address ahead of where it should be when u return from that call.
Dylan, John and I looked at this and found that all you have to do is add an address of 2 to the destination of a return instead of lea Ving it blank. Then it will be set to subtract by default during a Return.
Yay software fixes

[GISED_Link]

Or add some NOP instruction before the return ?

[LordDecapo]

Eww no.. that's waisted program lines. The less nops in ur program the better. If I can fix it with out adding program lines I much rather do that.
and the nop before a return wouldn't work.
right now when a Call is determined to be taken or not, the PC is already 6 lines ahead of where the first line of branch inst is. (Branch inst, is 3 inst word's long) so that makes the value that is pushed to the stack 2 lines to far in the program. So when u return, the PC value loaded wont be the line directly after the Call inst. It will skip 3 inst.. when I only need to skIP the 1 3word long Call inst.
so to fix this, u just hardcode the PC controler, to subtract 2 from the Return address, which is easy to do, u just have to say return, and put 0000010 in the Dest Address I'm the return inst. Then it will sub that and load up the very next line after he initial Call was placed.

[greatgamer34]

Very nice work around for that issue LD.

Although... Your app is still declined? Did you hack for OP?

==Hackering the 4channelz==

[LordDecapo]

IizR-L33t-x256-Hazx0r duh... I got staffs erwhere.

Lol thanks, it was kinda an AH-HA moment.. I inturupted john telling a story of something when I mentioned it lol.
then we refined the idea to that solution. XD
we r working more on RAM tonight,, nonvolital serial RAM. . Is a lot of work FYI, so many stupid bussing tricks to make it work on pipeline xD