07-02-2017, 12:27 AM
Me and Data are working on a hex ALU, i.e. inputs have 16 states, and I devised a common formula for make logic gates with n input states. Sorry if this post doesn't go into much detail, I will update it with a much more in-depth explanation.
OR gate: max(x,y)
AND gate min(x,y)
Now the XOR gate is a little tricky but I've found a formula: |x-y|. Now, when doing hex subtraction, compactors have the function max(0, back - side), only using one side. You can using max(x - y, y - x) when doing a hex XOR. Simply put, and XOR gate is the absolute difference between the inputs. The max function is easier, just combine all lines, highest signal strength wins. For the min function, first do invert on each input, i.e. 15-x, then combine (max) each line, then hex invert back again. This is actually the structure of a common and gate, just now using hex NOTs instead of binary NOTs. Please comment any questions!
OR gate: max(x,y)
AND gate min(x,y)
Now the XOR gate is a little tricky but I've found a formula: |x-y|. Now, when doing hex subtraction, compactors have the function max(0, back - side), only using one side. You can using max(x - y, y - x) when doing a hex XOR. Simply put, and XOR gate is the absolute difference between the inputs. The max function is easier, just combine all lines, highest signal strength wins. For the min function, first do invert on each input, i.e. 15-x, then combine (max) each line, then hex invert back again. This is actually the structure of a common and gate, just now using hex NOTs instead of binary NOTs. Please comment any questions!