AMISC 16 - 8 v1 (ISA)

[Matthijs de bruijn*]

Hello everyone,

I finished my ISA. It is called the AMISC 16 - 8 (Advanced Multiprocces Instruction Set Computing, 16 bit instructions for 8 bit proccesors).
It is going to run my cpu called the ALTEX CORE which is part of the Phaxios, a computer.
The ISA is my fourth. It can do a lot in one cycle. And suports multi proccesses. Not all instructions can be executed by every program for security.

Explaination.

division and multiplycations are done by the alu, a shift register and the barrelshifter. It can't multiply or divide in one cycle or instruction.
It basicaly does for instance by multiplycation: shift shift register and if shift out is 1 then add the accumulator to the second shifted value.
It sounds complicated, but it is simple. So for 15 times 15, you have to do one 15 in the shift register, then do the multiplication four times.

Two's complement is for making negative numbers positive. With the last two it did, it xors the flags and makes the thirth number positive or negative. So you can multiply negative numbers.

With immediate, you can load an 8 bit immediate or constante if you save it to an address.

Branch set 1 means basicaly set a variable to true if true, and after comparison, do logic operations with them so you can do a branch with the outcome.
Monitor means waiting for a flag while doing some stuf and jump to an addres if a condition is toggled

Subroutine interrupt option is for if the subroutine is one to handle interrupts. After this instruction has to follow the interrupt instruction.

Initialize is for the Initialize step, so the os can loadin instructions for the program.
Share means a shared address.

systemcall is for controlling programs.
Some options for what to do. Is it a driver program or a high priority program. Or is it the BIOS.

For the stop option you can stop the computer or program. first 4 bits means end of the file as you can see in the UNICHARS spreadsheat.

So, that was a big explaination. I think i will keep it like this, but maybe i am going to do some little changes.


What do you think of it, some tips?

Link: https://docs.google.com/spreadsheets/d/1...sp=sharing

GEGROET! (goodbye)

[Koyarno]

Hi matthijs,

I'm not sure how you do your jumps exactly. You specify in argument A only a 3 bit address or does C extend that? It seems kinda small.
Why two subtracts? you've got A and B and can reverse them however you like.
What is your end goal kinda? mine is to program sudoku and chess on one system. I would say there is no truly general purpose cpu but if you know what kind of programs you run
you might find some instructions you whish you had.

Btw, I would advise sketching a layout of the cpu completely before starting this. It seems grandour. Alot of projects fail due to the complexity of the Control Unit.
So, good luck.

[Matthijs de bruijn*]

Hey,

The address is not 3 bit, but is data in the GPRs. It should be a bit small  ( :.
I have two subtracts, so i can do reg - immediate and immediate - reg. Same for division.
I made the instructions for general purpose, because i want to do a lot, for som programs i don't need all instructions.

In my scetch book are lot of concepts for cpu's. For this ISA i made a cpu scetch to.


Bye

[Koyarno]

So you are telling me you have a 16 bit IS and you cannot make a 8 bit either relative or absolute jump within a single instruction?
Like 30% of code is a jump. And they almost never require the dataloop (address change) to interact with them. Especially on pipelined cpu's, a jump address as a pointer is very costly.

If you prefer a lot of functionality over performance then that is fine It is still your cpu ofcourse

[Matthijs de bruijn*]

It is simple, load in an immediate for A, then do the branch instruction.
I forgot the add to PC instruction : ). Now you can do it by the option "relative".

Nothing wrong :-).
Maybe i am going to add a branch predictor.