my first Computer progress

[ImaCreeperKaBoom]

update on my CPU thingy:
I finally finished the design of the main part of the CPU. I added a few things, cleaned up the overall look and made it a bit smaller and faster. the final specs are:
ALU white logic black
ICA with AND, NAND, OR, NOR, XOR, XNOR, NOT flags grey zero, even parity, odd parity, overflow, shift registers zero
add/subtract and multiplication by addition
5 ticks result of either addition or subtraction
3 ticks logic triggered 2 ticks before ALU result
7 ticks flag trigger its slower because the result is needed for the flags to be triggered

Cache L1: set one brown set two light grey
duel read quasi duel write 48 bits
3 ticks write. 3 ticks to save to result after it leaves the ALU
3 ticks read. 3 ticks to reach shift register read mux. therefor 6 ticks to read and send

Cache L2: lime
2 ticks write
1 tick read
1 tick to reach register write 2 ticks from read to write

shift registers red
2 ticks write
2 ticks shift
0 ticks to AX register

AX register: Purple
2 ticks write
0 ticks read

1.5 seconds for complete loop at the slowest going through L1
1.1 seconds for complete loop at the fastest going through L2
therefor the longest multiplication is shift register's last bit is active sine L2 is used for multiplication 1.1x8 is 8.8 seconds for the longest result. I plan on having a dedicated multiplier input so it can do the equation faster than waiting for the CU to read the next line since the clock is going to be at least 3 seconds probably. since it only takes 1.1 seconds to give a result no since waiting 24 seconds for the CU to do all the instructions if that makes since Smile  

external ALU output: green
2 ticks form result
external ALU input: pink
3 ticks to be written in cache

I added an external output for each cache 5 ticks to leave the output mux orange bus lines
I stream lined the design its flat on top and bottom and looks very organized and neat Smile

over all size 27x54x22  32076 blocks cubed