04-27-2015, 05:36 PM
Danke :3
Here's the finished data loop; it has all ALU functions, immediate muxing, and mapped registers ready to go for control logic. Also, there's a bus leading out that should be able to connect to up to 64 RAM addresses which I'll probably implement last. (also, I probably won't use all 64 of them
)
![[Image: 1dxDsSg.png]](http://i.imgur.com/1dxDsSg.png)
![[Image: Na3bTob.png]](http://i.imgur.com/Na3bTob.png)
Here's the finished data loop; it has all ALU functions, immediate muxing, and mapped registers ready to go for control logic. Also, there's a bus leading out that should be able to connect to up to 64 RAM addresses which I'll probably implement last. (also, I probably won't use all 64 of them
)