I am actually building something. Probably. (I've tried this before and it didn't go so well, but now I'm on break and I have nothing better to do).
Thus, welcome to the IABS ("Ice is Actually Building Something") CPU! As a consequence of my absences during which I had essentially zero exposure to CPU architecture, this will probably be a pretty nubby CPU to get my feet a bit wet again, especially compared to the pipelined crap that appears to be in style nowadays. It will run on separately-programmed ROM (I know, I know. If you stopped reading here I don't blame you) and use a variant of the RISC-16 IS that I have designed to work at least a little bit smoother on a minecraft CPU. In particular it implements more logical functions within the ALU so that operations like XOR don't necessarily take 5 or 6 cycles with NAND logic.
I'll try and post the IS and development pics here as (if) they get completed.
EDIT 1: Here's the IS; spoilers don't seem to work so this post may get a bit long.
![[Image: Ul8SoyF.png]](http://imgur.com/Ul8SoyF.png)
A few notes:
1) I genuinely apologize for the presence of HALT in an otherwise somewhat-professional-looking IS. Combining NAND and ADD into a single more versatile command leaves room for an additional command, and since I'm mainly going for programmability and practicality rather than innovation in this build I added a user interaction command rather than some esoteric branching condition.
2) I could have had sixteen ALU operations, but these are made so that any basic operation can be done in 2-3 clock cycles (which is plenty, and a hell of a lot better than the seven it would otherwise take to do XOR). Also no Minecraft program is ever going to use software nonimplication or whatever.
Thus, welcome to the IABS ("Ice is Actually Building Something") CPU! As a consequence of my absences during which I had essentially zero exposure to CPU architecture, this will probably be a pretty nubby CPU to get my feet a bit wet again, especially compared to the pipelined crap that appears to be in style nowadays. It will run on separately-programmed ROM (I know, I know. If you stopped reading here I don't blame you) and use a variant of the RISC-16 IS that I have designed to work at least a little bit smoother on a minecraft CPU. In particular it implements more logical functions within the ALU so that operations like XOR don't necessarily take 5 or 6 cycles with NAND logic.
I'll try and post the IS and development pics here as (if) they get completed.
EDIT 1: Here's the IS; spoilers don't seem to work so this post may get a bit long.
A few notes:
1) I genuinely apologize for the presence of HALT in an otherwise somewhat-professional-looking IS. Combining NAND and ADD into a single more versatile command leaves room for an additional command, and since I'm mainly going for programmability and practicality rather than innovation in this build I added a user interaction command rather than some esoteric branching condition.
2) I could have had sixteen ALU operations, but these are made so that any basic operation can be done in 2-3 clock cycles (which is plenty, and a hell of a lot better than the seven it would otherwise take to do XOR). Also no Minecraft program is ever going to use software nonimplication or whatever.