03-05-2015, 07:37 AM
(This post was last modified: 03-05-2015, 04:49 PM by Apocryphan.)
Another method I'm looking into does use the rapid subtract. and only 1 comparator tick per subtract, and giving the remainder. no adjustments to divide by 2, any adjustment to the comparator will add to 2. With proper timing I believe it is possible to determine the tick length to equal the loop count, and even use these to determine common denominators and simplify fractions.
Odd or Even
Divide by 2, so in about 8 ticks it can take an input of 15 and tell you it is odd, 8 ticks is the max duration for any input (division loop only, relative to 1/2 input value), basic implies gate to trigger when the loop ends on odd, uses a conjoined version with a falling edge detector to signal when the output is ready. I borrowed a balanced ternary circuit to trigger 0 if even and 2 if odd. output is a 2 tick signal.
![[Image: vSMhva1.png]](http://i.imgur.com/vSMhva1.png)
![[Image: n6J3Xb1.png]](http://i.imgur.com/n6J3Xb1.png)
![[Image: YbdS2v0.png]](http://i.imgur.com/YbdS2v0.png)
Divisible by 3 (adjustable)
This is the same loop, only with a 1 plugged into the side of the comparator, the comparator flows so the subtraction would happen after the expected 2, so that those 2 will be the 1st and 2nd wire after each loop instead of the last. this gives us the option to pull the 1st wire and set it as the remainder if its less than the divisor.
![[Image: D3KqYIk.png]](http://i.imgur.com/D3KqYIk.png)
or there are always larger options for more accessible triggers, right row is 4,5,6 subtractive loops
and left row is 7 and 9.
![[Image: V9n38hM.png]](http://i.imgur.com/V9n38hM.png)
The loop count timing is simple in a sense, if it loops once the clock duration is the input duration, the standard being 2 ticks (i may attempt a 1tick input, should work fine). Every additonal loop will add 1 tick to the clock duration, so it all comes down to clock duration - 1 = loop count.
Odd or Even
Divide by 2, so in about 8 ticks it can take an input of 15 and tell you it is odd, 8 ticks is the max duration for any input (division loop only, relative to 1/2 input value), basic implies gate to trigger when the loop ends on odd, uses a conjoined version with a falling edge detector to signal when the output is ready. I borrowed a balanced ternary circuit to trigger 0 if even and 2 if odd. output is a 2 tick signal.
Divisible by 3 (adjustable)
This is the same loop, only with a 1 plugged into the side of the comparator, the comparator flows so the subtraction would happen after the expected 2, so that those 2 will be the 1st and 2nd wire after each loop instead of the last. this gives us the option to pull the 1st wire and set it as the remainder if its less than the divisor.
or there are always larger options for more accessible triggers, right row is 4,5,6 subtractive loops
and left row is 7 and 9.
The loop count timing is simple in a sense, if it loops once the clock duration is the input duration, the standard being 2 ticks (i may attempt a 1tick input, should work fine). Every additonal loop will add 1 tick to the clock duration, so it all comes down to clock duration - 1 = loop count.