Oh yeah the cpu's done, I'm gonna make another one soon. It's gonna be very similarly laid out, but will be much more optimised with twice as many pipeline stages and support for interrupts and some fancy code injection.
(I'mma bypass the main program flow with a preloaded hi-speed instruction buffer to spam my dataloop and i/o stage with ops. It is going to be like microcode, but the code can be modified from external sources)
I might also do support for hardware register renaming/context switching. It would be nice to switch between two protected register banks.
(I'mma bypass the main program flow with a preloaded hi-speed instruction buffer to spam my dataloop and i/o stage with ops. It is going to be like microcode, but the code can be modified from external sources)
I might also do support for hardware register renaming/context switching. It would be nice to switch between two protected register banks.