Magic's Stoopid CPU

[Magic :^)]

Ok, so I've gone through my arch and IS more, and have come up with a pretty interesting system

So, a lot of instructions in my IS would make more sense as double-width instructions, but doing that would slow down the whole system in a lot of cases.
This is because the time taken to decode a register would be considered every time, even if I was performing the same op with the same registers. (This is a minor example)

So, I designed my IS so that the second half of a double-width instruction can be executed independently

e.g. my alu ops look like this:

[(A reg)(!A)(B reg)(!B)] [(C reg)(OR)(FC)(Cin)(SHR)(Pop)]

The next op would go the same way.

but, if I didn't need to change the source registers afterwards (e.g. A+B=A works with this arch),
I could do this op by itself:
[(C reg)(OR)(FC)(Cin)(SHR)(Pop)]

also, I am doing the cpu async, so the first half will be a LOT faster to resolve than the second half.
e.g. <5 ticks and 10 ticks respectively.

Also note that I put the inverters in with the first (reg load) op. They would have added 1-2 ticks to each op if I put it with the second part of the instruction

ok, here's some tentative specs:
(spoilered because the info is slightly outdated... It still is worth a read though )

My IS is now 11 bit

Supports up to 8 peripherals, with 8-bit data and addressing.
I have an address register that I can increment after a read or write op
The i/o system can read directly into the address register, to enable pointers

My dataloop is 10 ticks. Decoding and stuff takes longer, but that's explained above.
The dataloop has 6 dual-read registers.
It can read from two special-purpose registers for immediates or i/o fetches. They are special, I'll explain later.
There is a single-read 6-deep hardware stack.
There's a single-read flag register. It can take external status flags easily.
All these can be accessed from a 3-bit address :3

8-bit immediates are supported.


The special purpose registers are connected directly to the alu, one on each side. The SPRs can be written to from the imm instruction or the i/o read instruction.
In those instructions you specify whether you want to write to one, or both of the SPRs.
Writing to both essentially makes them dual read.
Writing to one makes that value available to the side you wrote to.
e.g. writing to SPR 1 will make that value available to the A reg's SPR address, and writing to SPR 2 would make the value available to the B reg's SPR address.


If the (Pop) bit is 1 during an alu op, the stack deletes one item. It does not read from it.
Peeking at the stack is treated like a normal register read, so to perform an actual Pop, you perform an op while peeking at the stack with the Pop bit set to 1. In that case you will also automatically peek at the next entry in the stack
Obviously, you could also pop the stack without reading from it to delete an entry.

Timing-wise, pop triggers after the write op, so you can write to nothing by writing to the stack with the Pop bit enabled. I don't know why you would want to do that, but you can

currently, writing to reg address 000 does nothing... It would be very easy to implement a function here, but I won't add anything until I come up with something the system actually needs.

yup i think that's it for now :3