I have a different concept for FIFO memory. It involves a read pointer amd a write pointer.
When you push data, it saves it to the memory at the pointer, then increment the pointer by 1 (overflows at the last address of the queue). I haven't developed any logic for if the queue is full yet, but you can probably easily do so using the existing circuitry involved with the read conditions.
When you pop data, it involves a bit of conditional logic. If the read pointer isn't the same as the write pointer, then read the data at the pointer and increment by 1 (same pointer overflow as above). If it is the same, then some other action must be taken (return zero, or maybe save a 1 to a flag register) and it does NOT increment the pointer.
I have made a hardware implementation of this concept that works with virtually any memory system with read/write functions. It involves a couple of shift registers connected into themselves for the pointers, where each individual output is connected to a read or write trigger on a memory cell. There'so also a bit of logical circuits (mainly AND gates) connected between the two shift registers for preventing reading from an empty queue.
When you push data, it saves it to the memory at the pointer, then increment the pointer by 1 (overflows at the last address of the queue). I haven't developed any logic for if the queue is full yet, but you can probably easily do so using the existing circuitry involved with the read conditions.
When you pop data, it involves a bit of conditional logic. If the read pointer isn't the same as the write pointer, then read the data at the pointer and increment by 1 (same pointer overflow as above). If it is the same, then some other action must be taken (return zero, or maybe save a 1 to a flag register) and it does NOT increment the pointer.
I have made a hardware implementation of this concept that works with virtually any memory system with read/write functions. It involves a couple of shift registers connected into themselves for the pointers, where each individual output is connected to a read or write trigger on a memory cell. There'so also a bit of logical circuits (mainly AND gates) connected between the two shift registers for preventing reading from an empty queue.
I'M BAAAAAAACK!