Trecar's CPU 01

[Trecar]

Better late then never, eh? I started with this right after getting builder in January 2017 and constructed it up until about June. In November I added I/O. In that timeframe I finished school, turned 18, moved out and started studying at a Uni so i kinda forgot to post about it here.
It's an 8 Bit 3 Operand CPU with a 16 Bit Instruction width, 8 Tick 4 Stage pipelined. There are 8 GPR's (Arranged in Simulated Dual-Read), 32 Bytes of Ram and a 64 Word Instruction ROM (Yes, it is torch, forgive me, i wanted 128 Bytes and it was my first CPU so i went with that. It is pretty compact though.)


Some things to note here, first of all probably why the hell is the LSB on the left? Well, um, that happened. Sorry, won't happen again. I am quite proud of the forwarding, though i am not sure anymore whether it also works for Inputs and whether you can stall Outputs. I do think so because i didn't post a sign anywhere that said otherwise, it's been a year. Sorry. AddCarry was broken once buit I think i fixed it again.

Now you may notice these two special Bits at the BRZ Instruction. These turned out very handy when programming it and could sometimes speed things up substancially. You do not have to use them tho to write a working program. It will probably help you a lot though.
The IMM Instruction for every ALU Op is also quite useful, which was actually really easy to implement with a 3 Operand design.
The RAM pointer thingy might look awkward at first, but it can be used quite neatly: Often you iterate thru the RAM when using a pointer, which you have to increment. If the Instruction previous to the swap is the pointer increment you have the pointer loaded right away and do not have to sacrifice an instrcution to make the pointer work (You will get the value before incrementation as the Adress).
I know the Adr Bits for IO are inconveniently located but as I said, it was added afterwards. Generally the IO looked really good on paper but turned out somewhat awkward afterwards, so if ya got any ideas on how to make a nicer IO system for a CPU feel free to sound off below.
Generally the ISA allows for short Programs:

Note: ns: Prev Inst NoSave; st: Stall;
RAM15 is Decimal Display

Fibonacci with Reset
00 limm r2 0
01 limm r1 1
02 add r1 r2 r1
03 swap r1 15 r3
04 xorimm r1 233
05 brz 1 ns st zero
06 brz 4      //Next 2 will execute! BRZ Delay!
07 add r1 r2 r2
08 swap r2 15 r3

Sequential Squares with Reset
00 limm r1 1
01 limm r2 1
02 swap r2 15 r0
03 add r1 r1 r3 //Lshift
04 add r2 r3 r2
05 brz2 Ntru //Not 255
06 addImm r1 1
07 addImm r2 1
08 brz 0

4x4Bit Multiplication
Written before Inputs. Hardcoded values.
00 limm r1 "A"
01 limm r2 "B"
02 xor r3 r3 r3 //fancy 0 coz yea
03 shr r1 r1
04 brz 9 st udf //Underflow
05 add r2 r2 r2
06 brz 3
07 nandImm r2 31
08 brz 12 ns st tru //255
09 brz 3
10 add r2 r3 r3
11 add r2 r2 r2
12 swap r3 15 r0

Pictures: 


Feel free to view it on my plot. If you want, you can write programs for it too. I have all my programs saved to its side so feel free to delete anything in the ROM. Make sure to not fuck anything up though. I always delete the torches manually and recommend you do so too. The control room is pretty self-explanatory. It creates quite the lag, so stop it when you are done!
As you can see there is a decimal Display. It can also convert to 2's C and its mapped to RAM Adr 15 (It is older than the IO).

Lastly, it's time to say thanks. This project was a shit ton of fun and i'm quite happy i managed to complete this challenge. When I got enough time again, I'd love to make a next one. That time with writeable Program Memory though. And a call Stack, And, And, And..... It will hopefully be completed before IntOREnet.
(I will not use simulated Dual-Read anymore. It's easy for the Dataloop, but control wiring is an absolute pain. I recommend investing into making a good Dual-Read Reg instead of this Chimera)

Parts Used:
CCA/Memory: Magic!
RShift: Koyarno
Binary to BCD: jeppevm87
2s Comp Converter: EEVV


Special Thanks:
EEVV - Teaching me, basically, everything. Memes aside, you are one fucking smart person.
Koyarno - DataLoop Concept
Tidal_Force - ISA Improvements
Paukkupalikka - Listening to me ramble on Discord
Whoever is hosting... erm.. Thanks to all Staff! <3

Lastly, a big Thanks to the Rest of the Community. ORE is an awesome place, and it's almost never boring here. Even if all I do nowadays is jump around on my CPU coz Uni is sucking the time needed to go after a big project again.

If you got any Questions ask below or hit me up ingame or in Discord. Last two Options will be a lot quicker.

P.S.: Hope you like my WordArt

[EEVV]

Finally! You know a lot of people on ORE do the opposite: they post the thread then "make" the CPU.

My favourite thing about this CPU is the endless improvisation that went into it. (Also I like your spreadsheet)

[Trecar]

Quick Note, I forgot to mention this: The RAM Pointer Thing essentially ORs the Register contents with the ADR you specify. So leave it blank. Or, maybe, at least in a CPU which had an actual call stack, this would be a very simple method of running mutiple instances of a method on different parts of the memory. Just that every instance might suck a Register.
But in theory you could. But in theory the Z3 had conditional branching too....

[Koyarno]

Would you be able to have relative addressing (adder between immediate & register) at some time cost?

[Trecar]

Not really, it is only an OR. Also as I said it works only for RAM. PROM adressing is all static. It could be added by grabbing a register value and macgyvering some cca somewhere... but you could also just write a program that adds ur immediate to a register value (takes only 1 instruction) and then laod from that adress (takes 2). So, combined 3.
Uhh, thats prolly what you meant.. yeah you can write a program doing that.
One could probably try do arrange a bus that similarly feeds a reg value to the program counter, in the current layout that would probably involve more than 1 sometimes "lost" instruction until it arrives...
But before you try that a quick glance at the bussing should very well tell ya that a reconstruction (=a new better CPU) is a far better idea...
Especially as the CCA used is by far not up to date in terms of speed or size, and the ram decoder is for bigger and laggier than it should be.
Fuck, if only I had the time too.

Some day, surely!

[Phase]

Nice job! I love the Word Art!

[Trecar]

Well, it's been a while. But this thread shall not die yet!
It is no secret that a torchrom is awful to program, and while I do not yet have the extreme time to fix that with a worthy successor, I had time to write an Assembler for this CPU.

What does it do? It takes code written in an ""Assembly-style"" language and converts it DIRECTLY into a Schematic that you can paste (-a!!!) into the CPU's ROM. This should allow anyone to quickly write and also test a program. In the meantime it also received a tiny hardware update. The control room has an indicator for when the PC is at instruction 0, and the add instruction can now also do +1 should you so desire. This, for example shortens sequential squares by one instruction. 

The Assembler can be checked out, downloaded and roasted at https://github.com/Trecar/MC-CPU01-Assembler
(Includes runnable .jar and source code)

The ReadMe should explain how to write code very well, so I don't wanna repeat myself to much here. It should make it fun to write programs for it, which is what I ultimately wanted. My point still stands, anyone can write and test code on the CPU if he wants to. No need to ask me.

Lastly, take a look at a Fibonacci program (also on GitHub):

Code:

LIM  sr1 0d
LIM  sr2 1d
SWP  lr1 15d  sr0
ADD  lr1 lr2  sr1
SWP  lr1 15d  sr2
JMP  3d
XORI ls1 233d
BZR  0d  ns st

Shoutout to Discord User Hilligan for setting me up with the perfect documents and libraries to undertake this little side-project!

Happy coding!