Rebuilt Diagonal Dataloop - "Godloop 2"

[QSmally]

Hi there!

As you might have noticed by the title, this post is about a dataloop I've been working on.

Godloop

The first "godloop" (by Smally) was created on October 8, 2016. The dataloop now rests on /pol. The loop is oddly timed, although it can run on a 6 tick clock cycle. The wiring was not so great, though. It's really clunky, not organised, and most of the time you would get lost in it. For that reason, I've decided, after two (and almost three) years, to rebuild it. After a break of about 5 months (don't ask why).

Specs

~ 7 Bytes Single-read Registers.

~ 8 Level Stack.

~ Universal bus between the stack and regs.

~ 4 Byte Cache.

~ Cache Controller.

~ 7 Tick ALU.

~ 8 Tick maximum clock cycle speed.

~ Everything timed, perfectly.

And indeed, the loop cannot be ran on a 6 tick cycle.


Credits
~ Volevi - Cache (I modified it a bit).
~ Unknown - Stack (I didn't build it though).
~ Unknown - Adder for the ALU.

Everything else, like the ALU, is built entirely by me.

Other Information

Feel free to use this dataloop in your CPU build, or just to mess around with. However, please give a credit notice on the build.
The warp to the loop is /warp #Dataloop.

Thank you all for the great support during this project!

[Koyarno]

Small, you are always good at building. I can see every unit you used :p. btw theres two color codes saying "set address" or something, i think one is supposed to be data no?
But ye the stack register is pretty public domain (multiple people build the exact design without outside influence).
And i was first with "godloop" but i dont consider that loop to be that good of a design anymore so you can have the name.
Oh and preferably you might want to latch the LRU unit but its not that great of a concern.

[konsumlamm]

Do you know that the cache was designed as BTB? Also, you didn't connect its output to anything... so it's technically no loop

[QSmally]

Small, you are always good at building. I can see every unit you used :p. btw theres two color codes saying "set address" or something, i think one is supposed to be data no?
But ye the stack register is pretty public domain (multiple people build the exact design without outside influence).
And i was first with "godloop" but i dont consider that loop to be that good of a design anymore so you can have the name.
Oh and preferably you might want to latch the LRU unit but its not that great of a concern.

Thanks, I guess. I haven't connected the Cache's output to anything, because people would prefer it connected to somewhere else. It's free to anyone to connect it their ways. And yes, I use the term "godloop" because you're one of my examples. I should change it, actually (It belongs to you).

Do you know that the cache was designed as BTB? Also, you didn't connect its output to anything... so it's technically no loop

And maybe it was designed for a BTB, but they basically have the same purpose. And as stated before, people might want it connected differently than I do, so I just left it that people can connect it their ways