(12-30-2015, 04:29 AM)ddthj Wrote: Currently Working

(12-30-2015, 03:10 PM)Iceglade Wrote: I once made a 1 bit CPU with a 2 function LU and 2 bit opcode, and one state-of-the-art 1 bit display

i think it qualifies

(12-30-2015, 09:51 PM)slugdude Wrote: My current CPU is crap at everything but the ISA is really flexible... A nightmare to program though until you pass that point where you love its quirks and love it. In terms of this particular CPU I built then here are the ratings out of 10 I'd give it:

P: 0. It does not actually calculate anything without using its memory maps. If you include them I guess around 6. It adds, subtracts, NORs, XORs, and rightshifts, but currently no mult/div or anything else more advanced. No relative jumps either.

E: 10. The whole ISA is very memory-map based so literally anything can be connected to it.

E: 0. It doesn't have any instruction to output or input but a register is mapped to a binary output so if you include that idk 2? It currently has no inputs but with the whole memory mapping thing it could be easily done - if you allow me to play the memory map card again you could say 10 .

C: 1. The current ISA supports a mere 16 lines of code which is pathetic. Nothing other than the PROM can be executed. The thing is, this CPU was a test of this ISA so I didn't want it to be a complex project.

U: Err, it works... Idk this is more a random number but 7?

U: 2. To someone new to it's ISA it's a bitch. Instead or having an add operation you copy the first value to reg 11, copy the second to reg 12, then read the value for the result of the 2 added. Similar mechanism for all logical/arithmetic operations.



In terms of it's specs:

9 tick clock, not pipelined. (In theory it should work with 8 but idk why the branching fucks up when I do that and I'm way too lazy to fix it). However in this time it can only either input an immediate value or copy a value from one register to another (or memory maps). Branching takes 3 cycles.

7 GPRs. Reg 0 is a ZR, regs 9 and 10 are for XOR and NOR atm, regs 11 and 12 for adding, 13 for rightshifting (once) and 14/15 for subtracting. Reg 1 is mapped to a binary display output but if you don't need to see anything until the program is over you can use it as a gpr until then.

The most optimised fib program I could make gave me one value every 5 cycles so 45 ticks. Although that includes three blank lines to sync it up... If you remove that you will have one value, 2 cycles later get the next, then 5 cycles later the next then 2 cycles... and so on.

PROM is 16 lines, each total 10 bits in length

It is an 8 bit CPU - although the adder and subtractor ignore the msb so that the cout can be stored in the msb of the result meaning the adder and subtractor are only 7 bit.


The CPU doesn't have a name. You can find it (I think) at '/warp slugcpu2' and the ISA it is based on is at '/warp SMI'.

(12-31-2015, 08:11 PM)MagicalGentleman Wrote: you should really refactor how clock speed affects the result by the way, One configuration I tried was 28 for a 10 tick clock and 23 for a 100 tick clock D:

Also, me and capo once came up with a cool way to benchmark cpus programmatically  using a modified version of fibb and the following rules:
You have 2 number displays, 1 display shows the current fibb value and the other shows the amount of times fibb has overflowed.
every time you overflow, you must start counting from the beginning again obviously.

The benchmark would be recorded by examining how many cycles it takes to do x iterations of fibb overflow, and multiplying that by your clock speed. The lower the number the better.
this test shows basically how well a cpu can do maths operations while giving feedback to a user. It covers the basics pretty nicely i think.

(12-31-2015, 08:11 PM)MagicalGentleman Wrote: you should really refactor how clock speed affects the result by the way, One configuration I tried was 28 for a 10 tick clock and 23 for a 100 tick clock D:

Also, me and capo once came up with a cool way to benchmark cpus programmatically  using a modified version of fibb and the following rules:
You have 2 number displays, 1 display shows the current fibb value and the other shows the amount of times fibb has overflowed.
every time you overflow, you must start counting from the beginning again obviously.

The benchmark would be recorded by examining how many cycles it takes to do x iterations of fibb overflow, and multiplying that by your clock speed. The lower the number the better.
this test shows basically how well a cpu can do maths operations while giving feedback to a user. It covers the basics pretty nicely i think.

(01-02-2016, 03:18 AM)2insanepeople Wrote: Here's a suggestion:
http://imgur.com/BSgDlgk
use a for loop. I don't care if they're too mainstream

(01-02-2016, 02:14 AM)Nuuppanaani Wrote: Define 'redstone cpu'. I do redstone on my IRL cpu, so I input that: 570,833.

(01-03-2016, 07:03 PM)Apuly Wrote: Whoever the fuck made that rating system needs to properly define clock speed and instruction.
You either ask for a clock speed, or instruction execution time, not both as the same.
Fokn 1 instruction can take multiple clock cycles.

(01-03-2016, 08:30 PM)ddthj Wrote:

(01-03-2016, 07:03 PM)Apuly Wrote: Whoever the fuck made that rating system needs to properly define clock speed and instruction.
You either ask for a clock speed, or instruction execution time, not both as the same.
Fokn 1 instruction can take multiple clock cycles.

Supposed to be instruction execution time - sorry

(01-04-2016, 06:29 PM)LordDecapo Wrote: *I may take a Crack at making a good rating system*