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IizR14 - Printable Version

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RE: IizR14 - greatgamer34 - 03-12-2015

Don't have any physical memory at address 000 lol

RE: IizR14 - fuirippu - 03-12-2015

Now, I'm disappointed...

I like my programs to start at 0 Sad

I want a ZR and mem address 0 !!!

RE: IizR14 - Magic :^) - 03-12-2015

register address 0, not program address xD

so then if you did $000 + $000,
and saved to $001

the value in $001 would be 0

RE: IizR14 - LordDecapo - 03-12-2015

#derail
#ZRftw

RE: IizR14 - fuirippu - 03-13-2015

Sorry... ZR is my new thing.


(03-12-2015, 09:49 PM)The Magical Gentleman Wrote: register address 0, not program address xD

Good. If it's gonna be called a register, I don't want it using up PROM or nothing !!!

Unless... hmmm.... are you trying to memory-map me out of my rightful share of bytes? Dodgy

RE: IizR14 - LordDecapo - 03-13-2015

#plznoderail

Any posts about that actually thread? LoloL
Gotta love OREs derail abilities

RE: IizR14 - Curiosity85 - 03-15-2015

What does the IS in IizR-IS stand for?

RE: IizR14 - Chibill - 03-15-2015

Instruction set

RE: IizR14 - LordDecapo - 03-16-2015

Yup lol

RE: IizR14 - LordDecapo - 03-31-2015

So guys, i finally am officially posting stats for IizR14. i have solidified most of these to be final. Only a couple things here and there are subject to change. 

-6tick clock (goes to 8 during serial transmissions, since I use 1tick/bit serial)
-6 stage pipeline
-128bytes of RAM(runs via Bytes and 8byte Pages so it can be connected to external storage)
-16-32 byte L1 cache (depending on ticks required)
-32memory mapped locations
-software and hardware based interrupt and exception support
-7 serial hardware ports (16bit sub addressing supported) with 1 being keyboard, 2 being network and 3 being display, so 4 universal ports.. all with interrupt support.
-8bit data width
-256lines of PROM
-64byte Instruction Cache (for external Inst. memory)
-16bit external Instruction addressing support with full Call and Return support.
-19bit external Data storage support (16bit page addressing, each page has 3 bit sub address delt with after a page is in RAM)
-And some more stuff I probably forgot to put in

The IS so far is this:

[Image: ASg6E0U.png]

The IS has some stuff that needs addressing and is subject to change, but this is it so far.


As i am closer to completion then ever, i will be making paperwork for this CPU on how it functions, how the individual ops will flow through the pipeline, and how the kernel/PROM will arranged. As the PROM will be used for built in functions that u can call to from a program stored externally.

so ya Big Grin  here it is, xD