My asynchronous pipelined CPU, aka AsPipe - Printable Version +- Forums - Open Redstone Engineers (https://forum.openredstone.org) +-- Forum: ORE General (https://forum.openredstone.org/forum-39.html) +--- Forum: Projects & Inventions (https://forum.openredstone.org/forum-19.html) +---- Forum: In Progress (https://forum.openredstone.org/forum-20.html) +---- Thread: My asynchronous pipelined CPU, aka AsPipe (/thread-4837.html) |
RE: My asynchronous pipelined CPU, aka As-Pipe - Magic :^) - 10-15-2014 I only have the data loop made, so alu ops, regs, and stack. no ram, no branching, no prom RE: My asynchronous pipelined CPU, aka As-Pipe - TSO - 10-15-2014 Yeah, like memory is the part that takes forever. You'll be done with that crap in like two hours. I time lined my computer at six months to a year. RE: My asynchronous pipelined CPU, aka As-Pipe - Magic :^) - 10-15-2014 Yeah, I still have to finalise the protocols I'm going to use for my memory system. I'm thinking of dealing with hazards on a per-peripheral basis. So if a request is sent to a peripheral, it has its own hazard checking logic and will hold back the result until it is safe to do so. I figure it will be easier than having one BIG hazard detection unit. It also makes addressing via pointers easier, as the system I'm imagining only cares about physical addresses. *shrug* I may change that plan. It'll work itself out once I start building stuff. RE: My asynchronous pipelined CPU, aka As-Pipe - LordDecapo - 10-15-2014 (10-10-2014, 01:10 PM)The Magical Gentleman Wrote: Anyways, I'm using microcode to translate 4-bit alu opcodes to the 5-bit codes it can interpret (I use the msb in my IS to indicate an alu op while in the main pipeline, so essentially 4-bit alu opcodes), so I can always replace one op with another with the slap of a torch Hey I do that I love my 4bit Op and 1 bit OpMode :> Also magical, Dylan Freemanz, and I looked at ur progress so far,, and we circle jerked on how much we liked it keep up the good work! Can't wait to see this done! RE: My asynchronous pipelined CPU, aka As-Pipe - Magic :^) - 10-15-2014 I am grinning like an idiot Oh yea, and the instructions are now being converted to 11 bit opcodes for the alu, it includes mode toggling and timing bits. The conversion still takes the same amount of time though (3 tick sync). I factor the decode/encode delay in to the timing section though, so the overall speed should still be pretty good. IS update: Code: [{ifT}{3-bit flag adr}] [{jmp adr}] 01001xxx aaaaaaaa RE: My asynchronous pipelined CPU, aka As-Pipe - Magic :^) - 10-16-2014 I uploaded screens to imgur. I am tired. Here: http://imgur.com/a/PsWOb RE: My asynchronous pipelined CPU, aka As-Pipe - greatgamer34 - 10-16-2014 why no OCD pack? RE: My asynchronous pipelined CPU, aka As-Pipe - Magic :^) - 10-16-2014 I'm getting on to that Don't you worry RE: My asynchronous pipelined CPU, aka As-Pipe - greatgamer34 - 10-16-2014 im working on a better resource pack based off of OCD, so it will be posted soon! RE: My asynchronous pipelined CPU, aka As-Pipe - Magic :^) - 10-19-2014 Heyo, I got distracted on friday and wrote a compiler for my (not yet complete) processor. There are still a few bugs (like needing a \n at the end of the file, and only outputting to the console) but it is now compiling everything properly. I will post it once I give it some polish for now, here's the fibonacci sequence in assembly to show the capabilities of the compiler: (I know having an if statement in fibonacci is stupid, but it's there for illustrative purposes XP) Code: # Fibonacci sequence in assembly code. Oh if you're interested in how I made the compiler, it's written in Python, and reads the source file one character at a time in two passes: once to log the macro/meta stuff, and then again for a proper compile and error checking. |