+- Forums - Open Redstone Engineers (https://forum.openredstone.org)
+-- Forum: ORE General (https://forum.openredstone.org/forum-39.html)
+--- Forum: Projects & Inventions (https://forum.openredstone.org/forum-19.html)
+---- Forum: In Progress (https://forum.openredstone.org/forum-20.html)
+---- Thread: My asynchronous pipelined CPU, aka AsPipe (/thread-4837.html)
RE: My asynchronous pipelined CPU, aka As-Pipe - Magic :^) - 10-10-2014
It just seems easier to program with b-a and !a available. They aren't necessary, but are useful for reducing the amount of lines of code. The alu is hooked up to be order sensitive, as otherwise I'd have to double the amount of load-type instructions.
So a is loaded first, then b is set up to be loaded next.
If you write to reg 000, you actually write the result back to the a register, and then b is set up to be updated next if required.
Because reshuffling the a and b registers for a sub takes time, and because clearing the b register and using NOR also takes time, using b-a and !a seems like a faster alternative to me.
RE: My asynchronous pipelined CPU, aka As-Pipe - TSO - 10-10-2014
What is !a? Is that like a'
RE: My asynchronous pipelined CPU, aka As-Pipe - greatgamer34 - 10-10-2014
! == not
ie; !a == not a == invert a
RE: My asynchronous pipelined CPU, aka As-Pipe - TSO - 10-10-2014
So it is exactly like a'
Many systems either NOR against the null flag, or have a hardware register inverter. They can also have distinct opcodes that are the same operations just with inversions of certain inputs if a really large instruction set is fine. The x86 set has a mix of all of the above.
RE: My asynchronous pipelined CPU, aka As-Pipe - Magic :^) - 10-10-2014
TSO that (second half) is how i implement it. The alu can do all logic ops using 3 possible outputs (xor, or, nor) and inverters in front of the a and b registers. !a is just inverting the a register and routing it into the main bus.
Anyways, I'm using microcode to translate 4-bit alu opcodes to the 5-bit codes it can interpret (I use the msb in my IS to indicate an alu op while in the main pipeline, so essentially 4-bit alu opcodes), so I can always replace one op with another with the slap of a torch
RE: My asynchronous pipelined CPU, aka As-Pipe - gera279 - 10-12-2014
NOR and NAND are the same thing, so one of those can be gotten rid of… Also, I would suggest choosing either XOR or XNOR, as they are normally used for testing and answers can be deduced from results of either.
RE: My asynchronous pipelined CPU, aka As-Pipe - TSO - 10-12-2014
NOR and NAND are far from the same thing.
AND is ab, but it is also (a' + b')'
NAND is (ab)', but it is also a' + b'
OR is a + b, but is also (a'b')'
NOR is (a + b)', but is also a'b'
Now your statement is that a'b'=(ab)'. Unfortunately, the inversion operator is not distributive across the unification of sets, this is easily shown with a Venn diagram.
I also remembered, you can get rid of a' by coding a NOR b and just making a and b read the same register. This operation would be no faster than a'. You can also put a' back into the instruction set, situated adjacent to the NOR function, and have a multiplexer at the NOR operator which either connects b or a to the second input. This only allows for a' to be found, though.
RE: My asynchronous pipelined CPU, aka As-Pipe - Magic :^) - 10-12-2014
due to how the alu loads values, your a NOR b method would take an extra cycle. It loads one value at a time. I know that method isn't ideal, but if I go back and change it it will take too much time and I can't be changing every little thing.
RE: My asynchronous pipelined CPU, aka As-Pipe - Magic :^) - 10-15-2014
I have the dataloop stage running now, I've tested most of the ops. I don't have any prom to plug in yet though, so the most i can do is loop one instruction. Namely: a=a+1
I wrote out the Fibonacci sequence in the meantime though:
Code:
#initial reg loads, calculate first 2 terms
0000| const
0001| 00000000
0010| const
0011| 00000001
0100| add 001
0101| regread 001
0110| add 010
#main loop
0111| regread 001
1000| regread 010
1001| add 001
1010| regread 010
1011| regread 001
1100| add 010
1101| jump
1110| 00000111RE: My asynchronous pipelined CPU, aka As-Pipe - TSO - 10-15-2014
WTF? How do you already have this thing built? It's only been like... one week