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+---- Thread: NLSC16 / CSC-16 My instruction set. (/thread-3314.html)
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RE: NLSC16 / CSC-16 My instruction set. - jxu - 04-30-2014
I thought there was a noticeable omission of a jump (J) command. I'm basing my knowledge off of MIPS, I know it may not be the best option but if you choose to implement a stack, either hardware or software, you should include push/pop commands too.
RE: NLSC16 / CSC-16 My instruction set. - Nickster258 - 05-05-2014
Okay, so there are some current qwerks about my instruction set that need some attention so that it is in operable condition before I would strongly advice it to be used.
Some things like the omission of interrupts and the obvious incompatibility for a 10 bit immediate. I may need to add room for jump commands and other branch functions are not going to be a problem.(as I have room for 13 more xD)
RE: NLSC16 / CSC-16 My instruction set. - elliottjudd - 05-05-2014
I can't handle it nick, my futile mind is blown.
![[Image: tim-and-eric-mind-explosion-gif--41769.gif]](http://memeguy.com/photos/images/tim-and-eric-mind-explosion-gif--41769.gif)
![[Image: 8283819.gif]](https://p.gr-assets.com/540x540/fit/hostedimages/1390818877/8283819.gif)
RE: NLSC16 / CSC-16 My instruction set. - Jallen - 05-05-2014
I may be being dim witted, but where does the 6-bit address come from in the branch command? as far as I can work our, you use: 3-bit op code, 2x 3-bit register adresses, 4-bit branch condition code... that leaves (16-3-3-3-4=)3-bits... I'm confuzd
RE: NLSC16 / CSC-16 My instruction set. - Nickster258 - 05-05-2014
(05-05-2014, 02:44 PM)Jallen Wrote: I may be being dim witted, but where does the 6-bit address come from in the branch command? as far as I can work our, you use: 3-bit op code, 2x 3-bit register adresses, 4-bit branch condition code... that leaves (16-3-3-3-4=)3-bits... I'm confuzd
The branch address is defined in the register. One can LUI or ADDI+0 then save that data. To branch, it will simply read that data and save it to the counter register. So basically, write an immediate value and save it to a register. The comparing function would then compare/contrast the numbers, decide whether to branch or not, then write the immediate to the counter register.
I am working on this system a bit on my plot and I can show you next time I am online. It also works as a jump command.
Because of this, the computer easily supports up to 256 lines of ROM.
RE: NLSC16 / CSC-16 My instruction set. - Jallen - 05-08-2014
I figured that you can cover push/pop/relative (jumping/branching) in a single op code. If you loop the current state of the PC into the read slot of the register address of the PC. You then have an op code that saves the current state of the PC plus an immediate to a register.
EDIT: you actually don't even need that, you can just use the ADDi again as long as the current state is addressable as the read.
EDIT: It seems I have some misconceptions about push and pop. They require a stack to be implemented but it would still be useful to have these functions