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+---- Thread: CMOSprinkle's Super Compact Redstone Computer! (/thread-296.html)
RE: CMOSprinkle's Super Compact Redstone Computer! - CMOSprinkles - 07-03-2013
Ok, I finished the final design and the entire 3 tick adder is 22Lx2Wx8H, obviously not very compact. However, it is much more compact than Whiteley's 20Lx2Wx17H 3 tick adder! I'll add a download link here soon, provided that my computer doesn't overheat. I know that it will overheat if I try to build the adder on my plot, so maybe I'll try that later tonight when my computer has had time to cool down.
RE: CMOSprinkle's Super Compact Redstone Computer! - CMOSprinkles - 07-04-2013
Bad news, Minecraftforum user Jxu had apparently already come up with the 2 tick half adder I designed quite a while ago. His half adder generates the carry in 3 ticks, but it's practically the same design as mine and can be made to generate the carry in 2 ticks by using my method. He also managed to compact it to 4 long, so the Adder he designed is only 12 blocks long. Even though I modified it, I'm giving credit for the design entirely to him since he most likely already knew how to modify the carry and chose not to for size. So I apologize for the plagiarism and I will remove the adder from my plot when I get home tonight. This brings my plot back to being entirely empty, apart from my unidirectional vertical shift register which is not very impressive, so that's a bummer. Work is continuing on the computer though, I'm going to use Jxu's Adder along with Minecraftforum user Aelond's 3 tick Universal Logic Gate to make the ALU. That's the next big update, and it's coming soon, so keep checking for new updates on the computer!
RE: CMOSprinkle's Super Compact Redstone Computer! - Billman555555 - 07-04-2013
Hey CMO, Nice Designs, Specially the Adder.
After I Have Finished SAC Can U Possibly Help Me On SAC 2, Its Going To Be Faster, Meaner and Cooler *Literally*(Lots Of Ice). Anywho Can You Help Me Make SAC 2 Possibly 0.75 Hz, Maybe 0.8. If Not Don't Hesitate To Tell Me.(Also Thanks For The Help On The SAC Fourm
).Thanks, Billman555555
RE: CMOSprinkle's Super Compact Redstone Computer! - VirtualPineapple - 07-07-2013
You say its going to be programmable, what type of architecture are you going for to modify programs 'interactively' (Von Neumann or Modified Harvard)?. Also what is your desired memory capacity overall on the computer (Registers, RAM, external storage)?
RE: CMOSprinkle's Super Compact Redstone Computer! - CMOSprinkles - 07-07-2013
I'm using the typical Von Neumann architecture for this at the moment. I suppose that could change if I run into issues with the bottleneck, though I think that 10 ticks should be a reasonable goal even for a Von Neumann computer. As for the interactive element, I'm still working on how to support that. It will have something to do with the GPU's hit detection and it may involve a flag register. As for the memory; the CPU will have 4 General Registers as well as an 8 byte stack. The main memory will be expandable, instant wiring will make expansion simple, and I will look into memory mapped I/O as soon as I get the chance. The Program Memory will also be expandable in the same way. How many bytes of each I put in will depend on what I need for my programs, but I will probably start with something like 64 bytes of each. I will be using the swapping technique to save space in the main memory. These are just some of my goals with this computer, but it is still a long way from being finished. I'm still debating using a RISC instruction set, I don't like the way that some functions have to be executed by using multiple instructions. Thanks for the questions, feel free to keep them coming!
Hey Bill, your post must have sneaked in there, I didn't see it before. I would be happy to help with SAC or SAC 2! I may not have any solid designs for hardware components yet, but I am always willing to help with designing the architecture. If speed is your goal, I can tell you how fast each component needs to be, and I'm sure I can assist if you need help making any of the components function more quickly.
RE: CMOSprinkle's Super Compact Redstone Computer! - CMOSprinkles - 07-19-2013
Hey, just in case anyone is still watching this thread, just want to let you know that the reason production has stopped temporarily is because I am having major overheating issues with my laptop. I hope that soon I will be able I resume work again, my CPU v3 is going to be the next release (whenever that is) and it is going to be completely RISC compatible, much faster and more powerful than versions 1 and 2.
RE: CMOSprinkle's Super Compact Redstone Computer! - Xeomorpher - 07-20-2013
._. Hope you fix it!
RE: CMOSprinkle's Super Compact Redstone Computer! - Billman555555 - 07-23-2013
(07-07-2013, 01:30 AM)CMOSprinkles Wrote: I'm using the typical Von Neumann architecture for this at the moment. I suppose that could change if I run into issues with the bottleneck, though I think that 10 ticks should be a reasonable goal even for a Von Neumann computer. As for the interactive element, I'm still working on how to support that. It will have something to do with the GPU's hit detection and it may involve a flag register. As for the memory; the CPU will have 4 General Registers as well as an 8 byte stack. The main memory will be expandable, instant wiring will make expansion simple, and I will look into memory mapped I/O as soon as I get the chance. The Program Memory will also be expandable in the same way. How many bytes of each I put in will depend on what I need for my programs, but I will probably start with something like 64 bytes of each. I will be using the swapping technique to save space in the main memory. These are just some of my goals with this computer, but it is still a long way from being finished. I'm still debating using a RISC instruction set.Thanks good luck with 1 hertz,
Hey Bill, your post must have sneaked in there, I didn't see it before. I would be happy to help with SAC or SAC 2! I may not have any solid designs for hardware components yet, but I am always willing to help with designing the architecture. If speed is your goal, I can tell you how fast each component needs to be, and I'm sure I can assist if you need help making any of the components function more quickly.
Also I have slowed production on SAC and SAC videos due to
Stufz but I can help on this if you need anything done.
Also I recommend asking Craftriot about OISC, he is developing
It to help MC computers to advanced to the next speed.
RE: CMOSprinkle's Super Compact Redstone Computer! - CMOSprinkles - 07-23-2013
I'm assuming that stands for 'Optimal Instruction Set Computing', which is a very bold claim to make. Although, I also assume that it would be identical to MISC, 'Minimal Instruction Set Computing', which is a concept that has been done. Anyway, send me a link to his thread about it and I will look into it. If he does not have a thread for it, ask him to make one. Thanks Bill!
RE: CMOSprinkle's Super Compact Redstone Computer! - Billman555555 - 07-23-2013
(07-23-2013, 06:52 PM)CMOSprinkles Wrote: I'm assuming that stands for 'Optimal Instruction Set Computing', which is a very bold claim to make. Although, I also assume that it would be identical to MISC, 'Minimal Instruction Set Computing', which is a concept that has been done. Anyway, send me a link to his thread about it and I will look into it. If he does not have a thread for it, ask him to make one. Thanks Bill!Close it stands for Optimised instruction set computing,
Utilising IS that are less than 48 bits in length but behave
Like RISC instructions, A+B for example in CISC might take
2 or 3 instructions but in RISC or OISC it takes 1 instruction.
SAC utilising OISC has 40 or so bits of IS per line.