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+---- Thread: Easing my way back into CPU design and building (/thread-10874.html)
RE: Easing my way back into CPU design and building - Nickster258 - 09-14-2016
(09-14-2016, 12:16 PM)Matthew Wrote:(09-13-2016, 06:22 AM)Nickster258 Wrote: I find your ADDi very interesting.
Definitely tempted to do something similar to this for my next(hell, maybe?) project.
nick?... redstoning?... i cant believe my eyes
Shhhhhhhh its a secret.
RE: Easing my way back into CPU design and building - tokumei - 09-16-2016
I'm pretty sure this instruction set has been finalized, so now it's time to plan the actual CPU build to go alongside it! A couple of days ago, I drew this pretty diagram. Okay, maybe it's not so pretty. My wiring skills aren't that great, but I think I have figured out all of the major buses between components. The next step is building the individual components, then figuring tick speeds for each of them so I can (hopefully) synchronize easily.
RE: Easing my way back into CPU design and building - tokumei - 11-15-2016
Bump: Wow, I had totally forgotten about this project. I got distracted by school and some other projects, I'm going to start working on this again.
I made that diagram a lot more pretty, but now I can't find it anywhere. Going to re-draw it digitally.
RE: Easing my way back into CPU design and building - Chibill - 11-15-2016
rip
RE: Easing my way back into CPU design and building - LordDecapo - 11-16-2016
lol. the self bumb makes it so much better xD
RE: Easing my way back into CPU design and building - tokumei - 11-16-2016
You're welcome.
Update: Cleaned up the diagram a lot!
![[Image: vSEVQpQCP-gKF79anEBjq2LhIS9p7kw4hjgzblFI...35-h626-no]](https://lh3.googleusercontent.com/vSEVQpQCP-gKF79anEBjq2LhIS9p7kw4hjgzblFIyhb5mKoTk4PipJMuvi1kRF64V25QFwiaadWyDb_6VlqVlC5AiUgjCuIzr3h9YefuXzUQqFR8bcBmispTZxM3g1YuIb0C1FNnD2iCWZbEoPu7Xh9JGAyXR-9a4VoAraAFrhNvPpgj5EJtRwz_1FUJj_8su2UIWoBzsFxIN6IcUPsb25SbwuvIf7QwofP3ftXVTLDU3B8lCB2rGwuXs708of61-zxwAWf85GLhCLe1TLEjHS-CvazefLpQBp_Bt-TSJReF8ASjA90TxTjVdwITi1AhjkcMxIfaImc_AbygZJD9X8df_lKekeqhnbfsK83XY2i4oKr2ZXb8n9m6pPyubttjGyT5IOasDYIJUWsHN6bT8841m2u7cHLwMB7KtPtifjlQfsJgr4BBFnU6w4evc2EJY42U17NU1XX1QZF5Ay5U3-xnrRyiW-_DjZFq5AWdzaBtZoFCCEErWAntjmd8FhvB9oRJc6rIAgrW5jE7aSjjHDFUFkM-W6NOWxdrvzIF8pQlUm2zoLs9gPBO6c73dW0af57brxlmfQglaybRugJX-23UTghFpLsdNSvQ37OKH3xf4oWv=w835-h626-no)
And no, this is not how it will be laid out, that would be highly inefficient.
Next step: I am going to be working on how to optimize the instruction decoder. My favorite task because it involves computing sums-of-products and building logic arrays :3
RE: Easing my way back into CPU design and building - Chibill - 11-17-2016
Your image is dead....
RE: Easing my way back into CPU design and building - tokumei - 11-17-2016
Aw man, I had hoped google would let the public see. I guess not. The old link is an album that now has the new diagram. Click here if you are too lazy to scroll.
RE: Easing my way back into CPU design and building - tokumei - 12-25-2016
Update: The instruction decoder seems to be done! Now I will begin work on the ALU and memory units. My plan right now is to learn and use CCA.
RE: Easing my way back into CPU design and building - tokumei - 03-22-2017
Wow, it's been a long time since I've touched this project. BUT I am determined to finish this! Let's get back on track.
From what I can tell, I have most everything done: ALU, registers, external (swappable) memory, and program decoder all seem to work. I ended up using a 4-bit diagonal CLE, neworegs, and a custom vertical memory design. What needs to get done: clocking, synchronization (which are the parts I despise the most)