<![CDATA[Forums - Open Redstone Engineers - In Progress]]> https://forum.openredstone.org/ Sun, 26 Apr 2026 02:33:30 +0000 MyBB <![CDATA[3 Input Adder]]> https://forum.openredstone.org/thread-15775.html Wed, 06 May 2020 22:00:10 +0000 ASRS_]]> https://forum.openredstone.org/thread-15775.html
A friend of mine has figured out the logic of how to make a 3 input adder. Here is a diagram of the logic:
[Image: 2020-05-06_23.27.58.png]
So far, me and a group of people have been able to make a fully functional RCA:
[Image: 2020-05-06_23.26.15.png]
And also a fully functional vertical CCA:
[Image: 2020-05-06_23.25.34.png]
The problem is that the vertical CCA is a little slow, and we weren't able to figure out a good way to get it faster.
It uses a little different logic than the diagram since it has some CCA logic included, but theres probably a better way to implement it.
It would be interesting to see what you people would be able to do.]]>
A friend of mine has figured out the logic of how to make a 3 input adder. Here is a diagram of the logic:
[Image: 2020-05-06_23.27.58.png]
So far, me and a group of people have been able to make a fully functional RCA:
[Image: 2020-05-06_23.26.15.png]
And also a fully functional vertical CCA:
[Image: 2020-05-06_23.25.34.png]
The problem is that the vertical CCA is a little slow, and we weren't able to figure out a good way to get it faster.
It uses a little different logic than the diagram since it has some CCA logic included, but theres probably a better way to implement it.
It would be interesting to see what you people would be able to do.]]> <![CDATA[Survival Post Office]]> https://forum.openredstone.org/thread-15753.html Thu, 30 Apr 2020 06:45:06 +0000 Angry_Salmon]]> https://forum.openredstone.org/thread-15753.html OPEN AN ACCOUNT ON THE SURVIVAL NETWORK (SURV_NET) TODAY! 

The Surv_Net is a storage-minecart-based automated postal service for the @Survival server only! Send up to 26 stacks of items to friends (27*26 stacks maximum with the shulker box premium package!) from the comfort of your in-game home! 

Services Include: 
  • Installation
  • Maintenance
  • FAST delivery
  • et cetera... 
  • FIRST COME (WITH PAYMENT) FIRST SERVE!
  • For pricing, instructions, & information (and to test the system for FREE) simply: /warp surv_net (pictured below)
  • (One term/condition applies: Please be kind!)


.png   SURV_NET.png (Size: 795.23 KB / Downloads: 15) ]]> OPEN AN ACCOUNT ON THE SURVIVAL NETWORK (SURV_NET) TODAY! 

The Surv_Net is a storage-minecart-based automated postal service for the @Survival server only! Send up to 26 stacks of items to friends (27*26 stacks maximum with the shulker box premium package!) from the comfort of your in-game home! 

Services Include: 
  • Installation
  • Maintenance
  • FAST delivery
  • et cetera... 
  • FIRST COME (WITH PAYMENT) FIRST SERVE!
  • For pricing, instructions, & information (and to test the system for FREE) simply: /warp surv_net (pictured below)
  • (One term/condition applies: Please be kind!)


.png   SURV_NET.png (Size: 795.23 KB / Downloads: 15) ]]> <![CDATA[SRIS-16 CPU]]> https://forum.openredstone.org/thread-15619.html Sat, 25 Jan 2020 07:12:27 +0000 Endershadow]]> https://forum.openredstone.org/thread-15619.html
SRIS-16 (Simple RISC Instruction Set) is a 16 bit CPU. The memory bus, registers, and memory addressability are all 16 bit (hence the 16 in the name).

It has 16 registers. Register 0 is the null register and is hardwired to null. The remaining 15 registers are general purpose and can be used for anything.

It has 35 instructions which are detailed in the attached text file.

One of the nice features about this is that it can execute all instructions in a single clock cycle. The only possible exception to this would be the memory instructions, but that's entirely implementation specific. Another nice thing is that you load 16 bit constants into the registers as well as do relative jumps with 16 bit constants all while staying within 16 bit instructions. The way I accomplished this is by having an internal 8 bit register which stores the upper 8 bits of the constant and a dedicated instruction for setting it with an 8 bit constant. This 8 bit register is part of the flags register and so pushing/popping flag data onto/off of the stack also affects it. The lower 8 bits of the constant are encoded into the instruction as well as a bit which specifies whether to sign extend the lower 8 bits or use the special register as the upper 8 bits.

While there is currently no stack pointer for stack operations since it uses specialized stack memory, a future revision might allow for using normal memory for the stack.

Here is a color coded visualization of the instruction set

.txt   SRIS-16 ISA Revision 2.7.txt (Size: 6.27 KB / Downloads: 7) ]]>
SRIS-16 (Simple RISC Instruction Set) is a 16 bit CPU. The memory bus, registers, and memory addressability are all 16 bit (hence the 16 in the name).

It has 16 registers. Register 0 is the null register and is hardwired to null. The remaining 15 registers are general purpose and can be used for anything.

It has 35 instructions which are detailed in the attached text file.

One of the nice features about this is that it can execute all instructions in a single clock cycle. The only possible exception to this would be the memory instructions, but that's entirely implementation specific. Another nice thing is that you load 16 bit constants into the registers as well as do relative jumps with 16 bit constants all while staying within 16 bit instructions. The way I accomplished this is by having an internal 8 bit register which stores the upper 8 bits of the constant and a dedicated instruction for setting it with an 8 bit constant. This 8 bit register is part of the flags register and so pushing/popping flag data onto/off of the stack also affects it. The lower 8 bits of the constant are encoded into the instruction as well as a bit which specifies whether to sign extend the lower 8 bits or use the special register as the upper 8 bits.

While there is currently no stack pointer for stack operations since it uses specialized stack memory, a future revision might allow for using normal memory for the stack.

Here is a color coded visualization of the instruction set

.txt   SRIS-16 ISA Revision 2.7.txt (Size: 6.27 KB / Downloads: 7) ]]> <![CDATA[DLD (Digital Logic Documentation)]]> https://forum.openredstone.org/thread-15501.html Mon, 25 Nov 2019 05:18:47 +0000 IAmLesbian]]> https://forum.openredstone.org/thread-15501.html DLD (Digital Logic Documentation)
an idea for a collection of information on different topics within Digital Logic

Link to Project: https://drive.google.com/drive/folders/1...sp=sharing
Link to Index: https://docs.google.com/document/d/1pX54...BaZfI/edit


     For different topics within Digital Logic, I plan to have a document written explaining it in decent detail.  Anything from half and full adders to ISAs to memory circuits and maybe even GPU Design.  I put a suggestion form in the google drive folder linked above.  I don't believe you need a gmail account to view the documents or even submit the suggestion form, feel free to correct me if I'm wrong.  Below is an explanation of the layout of the DLD.
  • DLD Index - Think of it as a table of contents, it shows you the layout of the folders and documents along with whether the documents are completed or not.
  • DLD Dictionary - A collection of terms found throughout the DLD's documents, sorted by the document first mentioned then alphabetically.
  • DLD Additional Resources - Various links to other resources sorted by the folder or document they have the most relevance to.
  • DLD Suggested Change (Form) - A form anyone can fill out that can be used to suggest whatever changes you think should be implemented.
  • Folders [0] through [6] - The documents containing information on various topics within Digital Logic.
Beyond that there's not much to say.


If you have any questions or want to help build up the DLD's resources please leave a reply.]]> DLD (Digital Logic Documentation)
an idea for a collection of information on different topics within Digital Logic

Link to Project: https://drive.google.com/drive/folders/1...sp=sharing
Link to Index: https://docs.google.com/document/d/1pX54...BaZfI/edit


     For different topics within Digital Logic, I plan to have a document written explaining it in decent detail.  Anything from half and full adders to ISAs to memory circuits and maybe even GPU Design.  I put a suggestion form in the google drive folder linked above.  I don't believe you need a gmail account to view the documents or even submit the suggestion form, feel free to correct me if I'm wrong.  Below is an explanation of the layout of the DLD.
  • DLD Index - Think of it as a table of contents, it shows you the layout of the folders and documents along with whether the documents are completed or not.
  • DLD Dictionary - A collection of terms found throughout the DLD's documents, sorted by the document first mentioned then alphabetically.
  • DLD Additional Resources - Various links to other resources sorted by the folder or document they have the most relevance to.
  • DLD Suggested Change (Form) - A form anyone can fill out that can be used to suggest whatever changes you think should be implemented.
  • Folders [0] through [6] - The documents containing information on various topics within Digital Logic.
Beyond that there's not much to say.


If you have any questions or want to help build up the DLD's resources please leave a reply.]]> <![CDATA[The Nibble Byte - A Hex CPU]]> https://forum.openredstone.org/thread-15487.html Tue, 05 Nov 2019 20:29:46 +0000 IAmLesbian]]> https://forum.openredstone.org/thread-15487.html The Plan
- Include Multiplier and Divider Circuits (Divider also outputs Modulo)
- RISC because easier hardware (First CPU so easy is good)
- 29 Total Operations currently (I'll post a link to my ISA eventually)
  - 5 Arithmetic
  - 8 Bitwise Logic
  - 6 Memory (Includes send and receive mentioned further down)
  - 5 Control Logic
- 8 Hex Bits (Equivalent to 32 Bin Bits)
- 16 Registers (1 Hex Bit)
  - 4 Registers are used for the display (Basically just simple output)
- Functionality to send and receive data (IntOREnet now a thing)
- Not pipelined (Again this is my first CPU)

Main Roadblocks (Trying to design all circuits from scratch)
- Hex Multiplier is only 1 hex bit
- No Hex Divider design
- No Hex ALU design
- No Hex PROM design (Probably not too hard tho)

Other Stuff
- The CPU is being built on my second plot (/p v IAmLesbian 2)
- I'll put updates here (assuming I remember to)
- Any advice is appreciated and I'm open to questions and constructive criticism


That's all I've got, hopefully I actually get stuff done]]> The Plan
- Include Multiplier and Divider Circuits (Divider also outputs Modulo)
- RISC because easier hardware (First CPU so easy is good)
- 29 Total Operations currently (I'll post a link to my ISA eventually)
  - 5 Arithmetic
  - 8 Bitwise Logic
  - 6 Memory (Includes send and receive mentioned further down)
  - 5 Control Logic
- 8 Hex Bits (Equivalent to 32 Bin Bits)
- 16 Registers (1 Hex Bit)
  - 4 Registers are used for the display (Basically just simple output)
- Functionality to send and receive data (IntOREnet now a thing)
- Not pipelined (Again this is my first CPU)

Main Roadblocks (Trying to design all circuits from scratch)
- Hex Multiplier is only 1 hex bit
- No Hex Divider design
- No Hex ALU design
- No Hex PROM design (Probably not too hard tho)

Other Stuff
- The CPU is being built on my second plot (/p v IAmLesbian 2)
- I'll put updates here (assuming I remember to)
- Any advice is appreciated and I'm open to questions and constructive criticism


That's all I've got, hopefully I actually get stuff done]]> <![CDATA[ProjectRed/Redpower CPU]]> https://forum.openredstone.org/thread-14935.html Thu, 24 Jan 2019 03:48:48 +0000 gsholbert]]> https://forum.openredstone.org/thread-14935.html
basic ideas for the CPU:
  • fully pipelined
  • 16-bit RISC architecture
  • no copy/paste or specialized "operating system"
  • theoretical 1-clock operations (basic arithmetic)
  • Real 1-clock operations (bit shifting, Boolean functions
Possible avenues:
  • Computercraft for Rom, easy programming, and possibly RAM (not sure if the speed possible would be necessary for the RAM)
  • Computercraft for Graphical output, exploring feasibility of the mod's touchscreens for input
  • Full compiler based in lua for easy in-game programming
Things I would love assistance on for full realization of my dream (too much?) CPU:
  • Advice on what instructions i should/should not implement
  • assistance in any programming matters (definitely my weakness. There is a gap in understanding i can't seem to get to click on how to get from running the instructions and numbers to the programs seen on the screen)
  • Regarding above, in-game, non-lua programming of the computercraft components is well within my own capabilities
  • FEEDBACK! I want to advance the status of minecraft computers, and I do not claim to be any kind of expert in computer science. 
I can provide logism schematics of planned components as well as proof-of-concept implementations (I already have some of the former) as soon as I figure out if anyone is genuinely interested in seeing this project come to fruition. Thank you all]]>
basic ideas for the CPU:
  • fully pipelined
  • 16-bit RISC architecture
  • no copy/paste or specialized "operating system"
  • theoretical 1-clock operations (basic arithmetic)
  • Real 1-clock operations (bit shifting, Boolean functions
Possible avenues:
  • Computercraft for Rom, easy programming, and possibly RAM (not sure if the speed possible would be necessary for the RAM)
  • Computercraft for Graphical output, exploring feasibility of the mod's touchscreens for input
  • Full compiler based in lua for easy in-game programming
Things I would love assistance on for full realization of my dream (too much?) CPU:
  • Advice on what instructions i should/should not implement
  • assistance in any programming matters (definitely my weakness. There is a gap in understanding i can't seem to get to click on how to get from running the instructions and numbers to the programs seen on the screen)
  • Regarding above, in-game, non-lua programming of the computercraft components is well within my own capabilities
  • FEEDBACK! I want to advance the status of minecraft computers, and I do not claim to be any kind of expert in computer science. 
I can provide logism schematics of planned components as well as proof-of-concept implementations (I already have some of the former) as soon as I figure out if anyone is genuinely interested in seeing this project come to fruition. Thank you all]]> <![CDATA[CardIAC CPU]]> https://forum.openredstone.org/thread-14826.html Wed, 12 Dec 2018 23:20:05 +0000 Chibill]]> https://forum.openredstone.org/thread-14826.html CardIAC CPU.  

This version uses binary. I will also be building one that has a expansion to it allowing higher numbers and stuff. 

I will post more as I work on it.


My goal is to finish the basic version atleat by the end of this year.

I will also write a simple cross compiler to compile programs meant for the decimal version to my binary version. ( Which is already slightly better with 256 vs the decimals 99 memory cells.)]]> CardIAC CPU.  

This version uses binary. I will also be building one that has a expansion to it allowing higher numbers and stuff. 

I will post more as I work on it.


My goal is to finish the basic version atleat by the end of this year.

I will also write a simple cross compiler to compile programs meant for the decimal version to my binary version. ( Which is already slightly better with 256 vs the decimals 99 memory cells.)]]> <![CDATA[i8-Pentium - A CPU built by Smally.]]> https://forum.openredstone.org/thread-14723.html Tue, 30 Oct 2018 20:35:47 +0000 QSmally]]> https://forum.openredstone.org/thread-14723.html Hi there!

I've been working on a CPU for the last what was it... uh one and a half years now. I've been rebuilding, redesigning, and remodelling everything of it since it was first created. In fact, I've rebuilt it six times, and working on another rebuild at the moment. This rebuild will be the final product of the CPU, after the countless prototypes.

And as you can see, the name is kinda weird? "i8-Pentium" or "i8x" for short, what does it mean though? "i8" means "Instruction (and the data bus) 8)", so it says that the instruction and data-bus are 8 bits in length. And "Pentium"? Well, it's a kewl name, okay? pls dont copyright me for using intel name pls kthx bai Other than that, the "x" in "i8x" is just a placeholder for the "Pentium".

i8-Pentium
I made the first i8x video on September 16, 2017. This was the fourth rebuild of the CPU System. You can find the first video here, and the i8x Update playlist right here. And also, subscribe to my dead channel if you want to. As already stated before, I'm currently working on the seventh's rebuild of the CPU, and this will be the final one. I've got everything planned out, including the instruction set, registry sets & naming, memory, IO, storage... Everything.

Therefore I need your opinions on the CPU. You can warp to the CPU in its current state using /warp #i8x, and you can find the Instruction set sheet right over here. You can also find the Instruction set on the warp.

Specs
As I always do, I will run through the CPU specs. Here they are, although they can be edited a bit when time passes on.
~ Accumulator based ALU, includes:
~ - A, !A (from registers).
~ - Fwd A, !A.
~ - Fwd B, !B.
~ - Carry-in.
~ - Right-shift.
~ - DCC.
~ - OR.
~ 8 Registers (000 = Zero reg).
~ Pointer for addresses.
~ 32 bytes of PMemory.
~ 32 bytes of Memory.
~ 32 bytes *7 pages of storage (per page loaded in memory or pmem).
~ 3 bit IO addressing.
~ Scheduled and unscheduled interrupts.
~ 8 tick clock (at its maximum).
]]> Hi there!

I've been working on a CPU for the last what was it... uh one and a half years now. I've been rebuilding, redesigning, and remodelling everything of it since it was first created. In fact, I've rebuilt it six times, and working on another rebuild at the moment. This rebuild will be the final product of the CPU, after the countless prototypes.

And as you can see, the name is kinda weird? "i8-Pentium" or "i8x" for short, what does it mean though? "i8" means "Instruction (and the data bus) 8)", so it says that the instruction and data-bus are 8 bits in length. And "Pentium"? Well, it's a kewl name, okay? pls dont copyright me for using intel name pls kthx bai Other than that, the "x" in "i8x" is just a placeholder for the "Pentium".

i8-Pentium
I made the first i8x video on September 16, 2017. This was the fourth rebuild of the CPU System. You can find the first video here, and the i8x Update playlist right here. And also, subscribe to my dead channel if you want to. As already stated before, I'm currently working on the seventh's rebuild of the CPU, and this will be the final one. I've got everything planned out, including the instruction set, registry sets & naming, memory, IO, storage... Everything.

Therefore I need your opinions on the CPU. You can warp to the CPU in its current state using /warp #i8x, and you can find the Instruction set sheet right over here. You can also find the Instruction set on the warp.

Specs
As I always do, I will run through the CPU specs. Here they are, although they can be edited a bit when time passes on.
~ Accumulator based ALU, includes:
~ - A, !A (from registers).
~ - Fwd A, !A.
~ - Fwd B, !B.
~ - Carry-in.
~ - Right-shift.
~ - DCC.
~ - OR.
~ 8 Registers (000 = Zero reg).
~ Pointer for addresses.
~ 32 bytes of PMemory.
~ 32 bytes of Memory.
~ 32 bytes *7 pages of storage (per page loaded in memory or pmem).
~ 3 bit IO addressing.
~ Scheduled and unscheduled interrupts.
~ 8 tick clock (at its maximum).
]]> <![CDATA[729 bit overwriteable browseable shulker box inventory-based memory, expandable]]> https://forum.openredstone.org/thread-14691.html Sat, 20 Oct 2018 17:51:46 +0000 baslak98]]> https://forum.openredstone.org/thread-14691.html Just managed to cram mechanisms for write, delete and sort, pre-browse of shulker boxes, pre-browse items and reset minecarts functions as well as I corrected the internal hopper setup for various hopper timing mechanics I've learned building the ROM version. Just (hah) the control wireing and software (big one) remains.

729 bit overwriteable browseable shulker box inventory-based memory, expandable in magnitues of x729

based on measuring stackable vs all-different non-stackable items
three hopper cycles: data, ones and zeroes
data and items are kept in shulker boxes in minecarts with chests which unpack and pack along their way down the device until everything resets when the bottom minecarts/the "copy" is launched up again.
items are written from the side cycles to the central one which stores the sequence
side cycles have 27 items each (27 1s and 27 0s)
data cycle either copies itself and is read, or its items are sorted back into the writing cycles at the same time as we're writing (ie overwriting)
will be written to and read at constant 1b/0.4s, there will be no gaps in the output when exchanging shulker boxes (ref ROM version)
you can browse to the shulker box of interest, then to an item and start writing (or overwriting) from that point
planned config will be this x4 because 10bps output could be streamed over 1 wire

https://imgur.com/gallery/AAOxi0A

[Image: sOkbL8o.png]

[Image: 2WdMty7.png]

[Image: zAUaa8p.png]

[Image: 0NKrBji.png]

baslak98]]> Just managed to cram mechanisms for write, delete and sort, pre-browse of shulker boxes, pre-browse items and reset minecarts functions as well as I corrected the internal hopper setup for various hopper timing mechanics I've learned building the ROM version. Just (hah) the control wireing and software (big one) remains.

729 bit overwriteable browseable shulker box inventory-based memory, expandable in magnitues of x729

based on measuring stackable vs all-different non-stackable items
three hopper cycles: data, ones and zeroes
data and items are kept in shulker boxes in minecarts with chests which unpack and pack along their way down the device until everything resets when the bottom minecarts/the "copy" is launched up again.
items are written from the side cycles to the central one which stores the sequence
side cycles have 27 items each (27 1s and 27 0s)
data cycle either copies itself and is read, or its items are sorted back into the writing cycles at the same time as we're writing (ie overwriting)
will be written to and read at constant 1b/0.4s, there will be no gaps in the output when exchanging shulker boxes (ref ROM version)
you can browse to the shulker box of interest, then to an item and start writing (or overwriting) from that point
planned config will be this x4 because 10bps output could be streamed over 1 wire

https://imgur.com/gallery/AAOxi0A

[Image: sOkbL8o.png]

[Image: 2WdMty7.png]

[Image: zAUaa8p.png]

[Image: 0NKrBji.png]

baslak98]]> <![CDATA[My CPU]]> https://forum.openredstone.org/thread-14229.html Sun, 01 Jul 2018 20:41:35 +0000 PaukkuPalikka]]> https://forum.openredstone.org/thread-14229.html
This thread serves two purposes:
1. progress updates and possibly discussion
2. increasing the likelyhood of the project actually getting finished

Expecting to finish before August 1st 2019, but this may fluctuate in one direction or another.

More information soon [TM] (sometime next week).]]>
This thread serves two purposes:
1. progress updates and possibly discussion
2. increasing the likelyhood of the project actually getting finished

Expecting to finish before August 1st 2019, but this may fluctuate in one direction or another.

More information soon [TM] (sometime next week).]]> <![CDATA[Computer playing tictactoe!]]> https://forum.openredstone.org/thread-14199.html Sat, 23 Jun 2018 17:18:35 +0000 draftdragon21]]> https://forum.openredstone.org/thread-14199.html Was working on a simple 2 player tic tac toe game with win detection and such. Pretty simple stuff. However, I wanted it to be bigger and more crazy so I am almost finished building a custom AI to play against and it has a (fairly) decent speed for being just out of full blocks, dust, torches, and repeaters. As you can see on the pic that I am also starting to build another one that will be faster and more compact with the AI more build inside it instead of hanging on the outside. More progress will be posted later on with a world download.
https://imgur.com/a/yL6Q4BY


]]> Was working on a simple 2 player tic tac toe game with win detection and such. Pretty simple stuff. However, I wanted it to be bigger and more crazy so I am almost finished building a custom AI to play against and it has a (fairly) decent speed for being just out of full blocks, dust, torches, and repeaters. As you can see on the pic that I am also starting to build another one that will be faster and more compact with the AI more build inside it instead of hanging on the outside. More progress will be posted later on with a world download.
https://imgur.com/a/yL6Q4BY


]]> <![CDATA[How to build an FPU?]]> https://forum.openredstone.org/thread-14118.html Sun, 03 Jun 2018 13:32:17 +0000 LBSC]]> https://forum.openredstone.org/thread-14118.html <![CDATA[I need help (chunk loaders)]]> https://forum.openredstone.org/thread-14038.html Thu, 17 May 2018 15:48:46 +0000 Matthew]]> https://forum.openredstone.org/thread-14038.html
sneak peek
[Image: Wr2uB8n.jpg]]]>
sneak peek
[Image: Wr2uB8n.jpg]]]> <![CDATA[Finding Pi. (Revisted!)]]> https://forum.openredstone.org/thread-13358.html Sat, 09 Dec 2017 21:48:43 +0000 Chibill]]> https://forum.openredstone.org/thread-13358.html <![CDATA[The MMM (Triple M)]]> https://forum.openredstone.org/thread-13069.html Mon, 04 Sep 2017 02:33:48 +0000 SpiritTree]]> https://forum.openredstone.org/thread-13069.html Introduction
Hello, everyone, it is Tidal_Force in case you are unfamiliar with my forum name.

As builds get more and more ambitious, it has come to my attention that a large, centralized memory system would be useful, as it would allow ORE members to offload large data storage from their plot. It would also serve as an extremely slow, rudimentary network if it has to. However, its protocols will be extremely simple and not explicitly based on real-life systems.

I propose the Massive Memory Module (the MMM for short) to accommodate this need. It is something I have wanted to do for a while now as I will need a large storage system for my upcoming CPU. Below is a list of its protocols and how I will be implementing it.

Basic Operation

The MMM is a system that operates on 8 byte blocks of memory. The memory is stored in queues, which wraparound to provide non-erasing reads. There is a link to the basic structure of the memory system I will be using. It is binary and it approaches 6 blocks/bit.

https://imgur.com/a/zH08e

There will be 2 ^ 11 (2048) addresses. This provides a grand total of 16384 bytes of data that the memory will be able to store. The addresses will only be allocated to a particular user nominally once the system is set up.

Protocol

The MMM will only allow one user access to it at a time. I realize this is simplistic, but I do not anticipate the need for multiple data accesses for an already slow system. If the MMM is already being accessed by a user when another user accesses it, the MMM will deny the request of the second user. It will not hold their request as a pending operation. Each user of the MMM will be identified by a plot address. The basic format of serial data that one needs to send to the MMM is as follows.

[1 Bit: Request Access/Intialization][1 Bit: Operation][11 Bits: Address of Block][Optional 64 Bits: Data][Optional 8 bits: Plot Address]

This means that each access to the MMM will be either 21 bits for reading or 77 bits for writing. If you want to communicate with the MMM, I will provide a serial system for you.

Networking

I will be (if this project is approved) constructing a network that will act as a scaffold for basic operation of the MMM. This network may be replaced when more efficient networks are finished. Each user will communicate with the MMM through the use of a central bus. This bus will be locked in two situations:
  • An acknowledged request to the MMM until the MMM is finished processing the request.
  • A request to the MMM when it is not currently busy.

Although this implementation is inherently simplistic, it will make it easier for the project to be completed.

Concerns
  • I will need another plot to construct the MMM and its related data buffers.
  • I am worried about connecting plots together as it may require going through unapproved areas. This is the main problem and if anyone has solutions it would be incredibly helpful.
  • The access times may be in the order of minutes (600+ ticks).


    Conclusion

  • The MMM will provide for the growing need of massive storage in ORE. It will be able to store 16384 bytes of data and access them in 8 byte blocks. If anyone would like to share suggestions or criticism, I am more than happy to read them.
]]> Introduction
Hello, everyone, it is Tidal_Force in case you are unfamiliar with my forum name.

As builds get more and more ambitious, it has come to my attention that a large, centralized memory system would be useful, as it would allow ORE members to offload large data storage from their plot. It would also serve as an extremely slow, rudimentary network if it has to. However, its protocols will be extremely simple and not explicitly based on real-life systems.

I propose the Massive Memory Module (the MMM for short) to accommodate this need. It is something I have wanted to do for a while now as I will need a large storage system for my upcoming CPU. Below is a list of its protocols and how I will be implementing it.

Basic Operation

The MMM is a system that operates on 8 byte blocks of memory. The memory is stored in queues, which wraparound to provide non-erasing reads. There is a link to the basic structure of the memory system I will be using. It is binary and it approaches 6 blocks/bit.

https://imgur.com/a/zH08e

There will be 2 ^ 11 (2048) addresses. This provides a grand total of 16384 bytes of data that the memory will be able to store. The addresses will only be allocated to a particular user nominally once the system is set up.

Protocol

The MMM will only allow one user access to it at a time. I realize this is simplistic, but I do not anticipate the need for multiple data accesses for an already slow system. If the MMM is already being accessed by a user when another user accesses it, the MMM will deny the request of the second user. It will not hold their request as a pending operation. Each user of the MMM will be identified by a plot address. The basic format of serial data that one needs to send to the MMM is as follows.

[1 Bit: Request Access/Intialization][1 Bit: Operation][11 Bits: Address of Block][Optional 64 Bits: Data][Optional 8 bits: Plot Address]

This means that each access to the MMM will be either 21 bits for reading or 77 bits for writing. If you want to communicate with the MMM, I will provide a serial system for you.

Networking

I will be (if this project is approved) constructing a network that will act as a scaffold for basic operation of the MMM. This network may be replaced when more efficient networks are finished. Each user will communicate with the MMM through the use of a central bus. This bus will be locked in two situations:
  • An acknowledged request to the MMM until the MMM is finished processing the request.
  • A request to the MMM when it is not currently busy.

Although this implementation is inherently simplistic, it will make it easier for the project to be completed.

Concerns
  • I will need another plot to construct the MMM and its related data buffers.
  • I am worried about connecting plots together as it may require going through unapproved areas. This is the main problem and if anyone has solutions it would be incredibly helpful.
  • The access times may be in the order of minutes (600+ ticks).


    Conclusion

  • The MMM will provide for the growing need of massive storage in ORE. It will be able to store 16384 bytes of data and access them in 8 byte blocks. If anyone would like to share suggestions or criticism, I am more than happy to read them.
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