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+---- Thread: DIO 2, my new CPU project (/thread-6002.html)
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RE: DIO 2, my new CPU project - Magic :^) - 03-25-2015
that x port will just be handled differently by the hardware than the other ports.
it holds pointers and this port can also be used to pass immediates to the dataloop's registers.
It is a special port because of the above reasons, and also because it is the only port you can't point to with a pointer.
(no pointing to pointers)
and yeah, it is mostly going to be used for I/O stuff. This port will also be faster to access than main RAM though, so you could also use it like a small amount of "fast RAM"
I'm thinking of holding 8-16 pointer regs in this port. Probably 8 due to size constraints.
I may or may not add simple increment and decrement ops for the pointers. It would be really nice for iterating through arrays, but it is also a bit awkward to implement :/
I might use CCA based pointer registers?
I'll probably include the stack in this port aswell, as I only need 1 address location for that. It would also give you the bonus of being able to use the stack as a pointer
RE: DIO 2, my new CPU project - Magic :^) - 03-25-2015
eh so new port setup, with some empty spaces:
Code:
000: RAM
001: Special (pointers, stack, immediates)
010: ?
011: ?
100: Serial Port 0
101: Serial Port 1
110: Serial Port 2
111: Serial Port 3any suggestions for the ?s or anything else?
RE: DIO 2, my new CPU project - Magic :^) - 04-02-2015
still ironing out the final form of my internal data busing. I'd love to be able to treat the dataloop as just another port location and allow data transfers between ports without going through the loop first, but... that may be hard.
RE: DIO 2, my new CPU project - LordDecapo - 04-02-2015
Not too hard, well at least in diagnal, not sure about vertical, try using a common data buss that only samples from the reg read, and writes to register via a different wire., (yay read enables!)