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Magic's Stoopid CPU - Printable Version

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RE: Magic's Stoopid CPU - Magic :^) - 02-10-2015

OOh what's this?

I have a fetch time prediction unit installed! It looks at the current address of the prom +1 and compares it to see if it will be a fast or slow decode time :3
Lookahead on the left, current address on the right:
[Image: 7B7ga6j.png]

And look! I'm almost done the main part of the CPU, I have to figure out the optimal timing for my instructions here... but once I figure it out, the cpu will be able to carry out all the main ops Wink
[Image: rGK1nCF.png]

I just have to get going on the branching stage now, I'm putting it in the middle of my prefetch buffer. It's going to be doing some speculative prefetching too :3

RE: Magic's Stoopid CPU - LordDecapo - 02-11-2015

Yay for dynamic branch prediction.. I think you and I are the only ones who currently have it xD

RE: Magic's Stoopid CPU - Magic :^) - 02-14-2015

Here's a tentative list of ops and the syntax they will use in asm:

Code:
regLoad (!)r1, (!)r2
regWrite r3, (alu opcode)
immLoad (8-bit immediate), (to SPRs OR ioReg)

ioRead (address source), (peripheral address), (result register)
ioRead+INC ...

ioBGRead (address source), (peripheral address)
ioBGRead+INC ...

ioWrite (address source), (data source), (peripheral address)
ioWrite+INC ...

buffRead (peripheral address), (result register)
buffRead+INC ...

jump (8-bit jump address)
call (8-bit jump address)
ret (8-bit jump address)
brIf (8-bit jump address), (condition)


////////////////////////////////////////////////

alu ops:
add, sub, and all bitwise stuffs
shift right can be done in the same op as all others
shift left supported via arithmetic shift.

conditions:
If0
Sign
Cout
Overflow


RE: Magic's Stoopid CPU - Magic :^) - 02-18-2015

Oh yeah the cpu's done, I'm gonna make another one soon. It's gonna be very similarly laid out, but will be much more optimised with twice as many pipeline stages and support for interrupts and some fancy code injection.

(I'mma bypass the main program flow with a preloaded hi-speed instruction buffer to spam my dataloop and i/o stage with ops. It is going to be like microcode, but the code can be modified from external sources)

I might also do support for hardware register renaming/context switching. It would be nice to switch between two protected register banks.

RE: Magic's Stoopid CPU - Spidermy9 - 02-18-2015

Love the time thingy Smile i remember me and i believe hawk also did something like this, but never really implemented it in a good fashion

RE: Magic's Stoopid CPU - LordDecapo - 02-23-2015

The dual register banks is helpful, but I have played with that idea before, and it's a little... picky sometimes lol. try using 15 instead of 7 registers, and make some of the special purpose.
just a thought Smile

RE: Magic's Stoopid CPU - Magic :^) - 02-23-2015

Yeah, I have a lot of stuff to improve in the new version. The arch is still similar, but only in spirit xD

I'm going for some speedup techniques for the instruction pipeline too. I'll elaborate on it later.

Also working on better i/o hardware. So far so good!
I got me some 1 tick/bit with input buffering so I don't drop bytes.

I'll try for 16 registers, but I'm not sure if I can get a low tick loop out of it....

I might be able to do the context shifting by having every bit of the register actually be a 2-bit barrel shift. Hmmmmnn

RE: Magic's Stoopid CPU - LordDecapo - 02-23-2015

That could work, I'll be on later if you wanna TS and talk about it. I'm curious to here the new upgrades and more in depth thinking as to what the changes do.

RE: Magic's Stoopid CPU - Magic :^) - 02-23-2015

I won't be able today, but maybe tommorrow Wink

My instruction queue optimisation would really only be explainable with a diagram though xD

RE: Magic's Stoopid CPU - LordDecapo - 02-24-2015

Kk, diagrams are always helpful xD
I'll be on today after work and I change my dad's serpentine belt on his truck.
When ever ur on we can talk about ur stuffs, got some idea about my stuffs I wanna run by u too.