MY most recent (mini) project has been the memory address decoder. Started and finished it today. This is the front view. (shown here with 256B of memory)


Top view.


View of output busses. The triangles are because the data input lines all had to be shifted exactly one to the right in order to be inline with the output lines.


Data input.


Address and controls. (L to R) bottom/top, selective read/read all, left/right select, read, write, address.


The address gets split four ways.


One decoder of my own simplistic and intuitive design (this is line 01111, #16 because the count starts at zero)


Some of the instruction set. It's a bit out of date, the CPU state (d) is no longer being considered, so z is six lines instead of five.


Some of the expected ALU operations and maximum allowed times. Most of these were calculated for an 8 bit ALU servicing a 16 bit computer, so many of the numbers are much lower now. I don't know which way AND and OR point because I just use * and +, but for this case, AND is pointing up and OR is pointing down.


16 bit insta-carry 4 tic adder/subtractor. I can speed this up by two or three ticks using some special logic tricks, but I haven't gotten around to it.


It uses Bennyscube's XNOR derived design.


A two bit example of the AND lattice for the Multiplier.


The eight bit version.


Bussing the multiplier. It uses lattice multiplication.


Least significant portion. (None of this was made with world edit because I hadn't downloaded it yet.)

Overflow portion. (Hand built) The use of the three tick adders makes this an 18 tick device, moving down to a one tick adder will make it 10 tick, accelerating the diagonal busses will bring it to 8 tick, and making the lattice instant will bring it down to 6 or 7 tick (depending on how instant you make the lattice.)


A single memory bit, again bennyscube.


A single register bit, I got it from a bennyscube video, but he said it came from someone else. (I only really watch bennyscube because I just need some occasional tricks to make things smaller, a good example is this d flip flop, which is not made from two nor gates and two and gates.)


Small memory block (64B)


Something I mentioned earlier, a hardware implementation of stacks. This was intended to be the run-time stack so that subroutine branching could be done easily. If you want more information about this, just ask.
Push control side.

Input side (inputs on ground)


Output side (also on ground)


Push mechanism


Pop mechanism


Register OR. Oddly enough, a zero tick inline output with stacked inputs is extremely difficult to implement, but I made it work. Took forever, though. I have the other Boolean operators, but none of them are worth mentioning because they were extremely easy to build.


The thing we've been waiting for. Below are my spawn chunks, if you look at my y altitude, it's 302, which was basically the minimum height you can view this thing in it's entirety from. The dimensions are roughly 128*127*132 blocks. The spawn chunks aren't entirely filled because it needs room for the decoder and data bussing. The bottom right corner takes the longest to address, an ungodly 42 tick process. The whole thing totals up to around a glorious 12KB (yawn), I'll check the exact value later, but all of it can be addressed. I can stack one more big block on there to make it 16KB, but I really don't have half an hour to kill at the moment (my laptop is completely useless for the entire time that the paste is occurring.)


Standing on it, 11 FPS. y=168


Same location looking up, 47 FPS.


Some views from y=1 to give you an idea of how big it is.