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+---- Thread: GG-ISA-16 (/thread-3205.html)
GG-ISA-16 - greatgamer34 - 04-21-2014
This is the GreatGamer-Instruction Set Architecture-16 Bit.
This is the ISA to kill all other ISA's
The first 5 bits are the OP Codes. That's right 31 instructions!
*Note* This is designed around Ntwede's ALU's capabilities. And it is a 2 OP SYSTEM!!!!
00000 Add
00001 Adc
00010 Sub
00011 Subb
00100 ADDI
00101 SubI
00110 Or
00111 Nor
01000 And
01001 Nand
01010 Xor
01011 Xnor
01100 Mov
01101 Up Shift-uses either the pointer in register b, or register b's address to shift A up to 7 times.
01110 Down Shift-uses either the pointer in register b, or register b's address to shift A up to 7 times.
01111 Rotate up-uses either the pointer in register b, or register b's address to shift A up to 7 times.
10000 Rotate down-uses either the pointer in register b, or register b's address to shift A up to 7 times.
10001 Mult-Hardware Multiplier
10010 Screen Op- uses IMM as what to do. It can Push, Plot, Reset Screen Register, and Reset Screen!
10011 Poll int-Uses either an IMM or a pointer in B as an address.
10100 JALR Direct- Jumps to a line from address in register B, or in the IMM.
10101 JALR Indirect-Jumps to a line from address in register B, or in the IMM.
10110 BEQ Direct- Jumps to a line from address in register B, or in the IMM.
10111 BEQ Indirect- Jumps to a line from address in register B, or in the IMM.
11000 BGT Direct- Jumps to a line from address in register B, or in the IMM.
11001 BGT Indirect- Jumps to a line from address in register B, or in the IMM.
11010 LWM Loads a Word from Ram, to register B.
11011 SWM Stores a word to Ram, from register B.
11100 LWI Loads a word, to B,increments stack pointer
11101 SWD Stores a word, from B, decrements stack pointer.
11110 Will be bit checking
11111 Will be bit checking
Next are 2 sets of 3 bits.
One set is For Read A/Writeback, the other set is for Read B.
This is a 2 Operand System!!
So for example, addition would be, A=A+B
the LAst 5 bits are the IMM.
Tadah!!
RE: GG-ISA-16 - VoltzLive - 04-22-2014
alex I have one word for you....
Parameters.
RE: GG-ISA-16 - greatgamer34 - 04-22-2014
Care to elaborate a little?
RE: GG-ISA-16 - LordDecapo - 04-23-2014
he means like in all those jumps/branching,,, all u need is the destination address in RAM, so u put that as B+5bitImm, (so u can have more RAM) then u use the 3bits that norm are RegA/writeback,, as conditions, so u can have 8 different kinds of branching, using only one of the 5bit opp code instruction,,, instead of like 8.
RE: GG-ISA-16 - Magazorb - 04-24-2014
Q.1 isn't that a 32 instruction IS?
Q.2 you said "GreatGamer-Instruction Set Architecture-16 Bit", i shall put focus on architecture, and ask where's the rest of it?
Q.3 How comes you have 2 bit checking instructions?
Does look quite good overall
although i prefer those that can do RRR and RRI instruction types more then this, this still looks pretty promising Nice work
