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+---- Thread: 1(?) tick Read, 2 (nope, 1) tick Write torchless, non-inverting memory (cell) (/thread-12715.html)
1(?) tick Read, 2 (nope, 1) tick Write torchless, non-inverting memory (cell) - Zijkhal - 07-19-2017
It basically works by weakening the output signal of the repeater-memory so that the OutputDisable stack can directly go into the side of the comparator, thus the 1 tick read (2 if we count the repeater needed for the OutputDisable signal, but if the OutputDisable is generated in-place from the adress, it may be eliminated)
[attachment=859]
If the furnace / chest / whatever is not full, some output will leak through, but if set correctly, it wont reach any critical parts. Upon withdrawing the OutputDisable signal, output signal strength is increased for a single tick by however strong the OutputDisable signal is at the output comparator.
If that one tick only output is a problem:
[attachment=860]
Edit: Looks like I got beaten to it
(07-28-2017, 08:41 PM)BigPigfootsie Wrote: I love how this same concept was implemented by me at the beginning of July
Ps.: as a bonus, I've made Magic's 2 wide register torchless, while I was triing to make mine 2 wide based on it (reluctant to bump as that thread is a year old)
[attachment=861]
just set the furnace / chest on the far right so that the comparator extracts a signal strength that just reaches the "exit" of the memory array, so while there is bleedthrough even if the OutputDisable is on, it wont be detected at the output of the whole block. (haven't tested, but should work)
RE: 1(?) tick Read, 2 tick Write torchless, non-inverting memory (cell) - Matthew - 07-19-2017
you should check out /warp d-memory on build
RE: 1(?) tick Read, 2 tick Write torchless, non-inverting memory (cell) - Zijkhal - 07-20-2017
Cool trick with the observers and rails, gotta remember that!
but: If I am not mistaken, that one cant read and write at the same time, because on writing, "ghost" outputs may appear, unless you keep powering the OutputEnable line, in which case it would take 2 ticks to read.
I have seen similar to mine, but never the same (unless I missed something), all either used the comparator to make it smaller by the signal strength shenanagins, or to be able to put the output on a common stack without them interfereing, and not to compensate for the loss in signal strength on the OutputDisable line.
Also, if that is 1 tick write, then mine is 1 tick read and write (plus mine does not invert). But I'm confused at this point, in my testing, I needed a 2 tick long pulse to write, as a 1 tick wont unpower the side comparator, am I misunderstanding something here?
edit: okayy, the side comparator needs 2 tick pulse, the one that actually stores the info only needs 1 tick. That can be done, but that may include some extra latency controller side.
RE: 1(?) tick Read, 2 tick Write torchless, non-inverting memory (cell) - Matthew - 07-20-2017
(07-20-2017, 08:12 AM)Zijkhal Wrote: Cool trick with the observers and rails, gotta remember that!
but: If I am not mistaken, that one cant read and write at the same time, because on writing, "ghost" outputs may appear, unless you keep powering the OutputEnable line, in which case it would take 2 ticks to read.
I have seen similar to mine, but never the same (unless I missed something), all either used the comparator to make it smaller by the signal strength shenanagins, or to be able to put the output on a common stack without them interfereing, and not to compensate for the loss in signal strength on the OutputDisable line.
Also, if that is 1 tick write, then mine is 1 tick read and write (plus mine does not invert). But I'm confused at this point, in my testing, I needed a 2 tick long pulse to write, as a 1 tick wont unpower the side comparator, am I misunderstanding something here?
edit: okayy, the side comparator needs 2 tick pulse, the one that actually stores the info only needs 1 tick. That can be done, but that may include some extra latency controller side.
Do you have discord? Also the observer based memory uses no comparators so... Unpowering the rails for 1 tick causes the observer to pulse if no data was written, unpowering the rail (not counting decoder output repeater) is instant so what your left with is a 1 tick "one way" inverter.
You never will read/write to the same cell at the same time so that problem doesn't exist.
Needing to invert inputs or outputs is not an issue, its actually preferred cause then you can take advantage of that in the memory cells and not need to make the first inverter on the AND gate for the read. - Taking advantages of inversions is fun af
RE: 1(?) tick Read, 2 tick Write torchless, non-inverting memory (cell) - Zijkhal - 07-21-2017
(07-20-2017, 10:22 PM)Matthew Wrote:(07-20-2017, 08:12 AM)Zijkhal Wrote: Cool trick with the observers and rails, gotta remember that!
but: If I am not mistaken, that one cant read and write at the same time, because on writing, "ghost" outputs may appear, unless you keep powering the OutputEnable line, in which case it would take 2 ticks to read.
I have seen similar to mine, but never the same (unless I missed something), all either used the comparator to make it smaller by the signal strength shenanagins, or to be able to put the output on a common stack without them interfereing, and not to compensate for the loss in signal strength on the OutputDisable line.
Also, if that is 1 tick write, then mine is 1 tick read and write (plus mine does not invert). But I'm confused at this point, in my testing, I needed a 2 tick long pulse to write, as a 1 tick wont unpower the side comparator, am I misunderstanding something here?
edit: okayy, the side comparator needs 2 tick pulse, the one that actually stores the info only needs 1 tick. That can be done, but that may include some extra latency controller side.
Do you have discord? Also the observer based memory uses no comparators so... Unpowering the rails for 1 tick causes the observer to pulse if no data was written, unpowering the rail (not counting decoder output repeater) is instant so what your left with is a 1 tick "one way" inverter.
You never will read/write to the same cell at the same time so that problem doesn't exist.
Needing to invert inputs or outputs is not an issue, its actually preferred cause then you can take advantage of that in the memory cells and not need to make the first inverter on the AND gate for the read. - Taking advantages of inversions is fun af
I have Discord
When I said ghost output on that, I forgot Observers observe any change, and not just powering up, derp.
That AND gate is for the Demultiplexer at the end, right?
RE: 1(?) tick Read, 2 (nope, 1) tick Write torchless, non-inverting memory (cell) - BigPigfootsie - 07-28-2017
I love how this same concept was implemented by me at the beginning of July
RE: 1(?) tick Read, 2 (nope, 1) tick Write torchless, non-inverting memory (cell) - Zijkhal - 07-28-2017
(07-28-2017, 08:41 PM)BigPigfootsie Wrote: I love how this same concept was implemented by me at the beginning of July
I just wanted to make a torchless 1 tick read memory and this is what I came up with
Since I have not found anything on the forums resembling this concept, I thought I'd put it here just in case
