Yes yes, i already know that theres already one of this:
http://tossha.com/rpl/
But, i think its pretty command-oriented, what i mean, is making a language, that can make computer science, here i have a snippet with the idea:
Code:
structure xor_gate(in A, in B)
return xor(A,B) # There are predefined gates
fin
structure rca(in A, in B, param in Cin, param out Cout)
xa = xor(A,B)
Cout = and(A,B)
y = xor(Cin,xa)
Cout += and(Cin,xa)
return y, Cout
end
rca(1,0,0)
This code will build an RCA bit. With all its logic.
In fact, it is really simple, using some schematics of already built gates, you can make an rca, like the one ive made above. It is really simple, xa equals to XORing 2 inputs, Cout equals to ANDing the same inputs. You repeat the process, but now with Cin and xa. You should have get it.
It is just a draft, any ideas are collected.
(02-04-2016, 06:35 PM)TheCrimulo Wrote: [ -> ]But, i think its pretty command-oriented, what i mean, is making a language, that can make computer science
W0T
How about we just make a C compiler for somebody's cpu?
Sounds a lot more interesting to me than creating our own language.
(02-04-2016, 11:10 PM)Apuly Wrote: [ -> ]How about we just make a C compiler for somebody's cpu?
Sounds a lot more interesting to me than creating our own language.
Yeah apuly! This is a great idea!
@crim, what you're actually suggesting with that example is a hardware description language.
I'd suggest making a place-and-route / synthesis tool for redstone which parses verilog code.
Depending on how feature-rich the tool is, it could actually be a pretty exciting development for the community. Imagine the coverage online of people generating open source verilog cpus in minecraft, just for the "cool" factor of seeing it all laid out in three dimensions.
You could even have 3 different PAR algorithms tailored to the different cpu building paradigms. (horiz, vert, diag)
If each version is optimised reasonably well, people could be able to contrast identical designs against different build styles.
I agree. We should either make a configurable C or Python compiler for Redstone CPUs.
Or do a verilog synth like magic mentioned.
I have a configurable assembler already mad, u just have to modify the couple dictionaries in the python code.
I should really refine it and make it cleaner. I have something that outputs AutoProgram format from the assembled code. But I haven't checked if AutoProgram still works.
I think C is still outside the scope of most builds, and that assemblers will need to be hand-coded by the cpu designer. While assemblers are straightforward to create, a general one could not possibly account for all the quirks of a given cpu. ESPECIALLY a minecraft cpu lmao.
e.g. delay slots, addressing modes, labels etc. need to be accounted for on top of just translating mnemonics to machine code.
my main worry is that a limited target assembler will influence a cpu designer to make similarly limited decisions. For example, I'm going to do my own because I want to be able to jump to a specific label with one instruction, and have the assembler decide which jump instruction to actually use. If it is a very long distance jump, it may even need to use another instruction or two for a larger position agnostic jump based on calculations using my program counter.
I had an idea for a super generic system with lots of custom variations. I will be making it for my GPU after i get it farther along in the building process. Then i will post an example of an IS config file you will load into it
i think it will be super useful for a broad spectrum of IS's and designs.
or even a basic python XD
(I am working on this. Its simple enough for some stuff. Plus has a built in AST praser.