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Hello people,
I was playing on build and Craftriot suggested a new
IS coding called OISC or 'Optimised Instruction Set Computing'
Utilising a larger number of bits in a Line of code than CISC but
Behaving just like CISC instructions. This is currently WIP but
Will be finished at the same time as SAC. You may implement
This ISC but you will need.
Code:
Dual read registers
Comparability of 15 to 255 RAM slots
ALU with 7 - 8 control bits
Multiple command control bits (If using GPU, serial, ect)
And a way to port this to CISC if required
A video will be coming soon with more SAC progress,
Bai.
Is OISC name is something you cam up with or the idea exists, becouse as far as I am aware of OISC stands for "One Instruction Set Computer" (aka Ultimate RISC). And my take on going CISC-like in MC computers is a big no, since we are trying to make computers faster now, in order to innovate stuff such as MC Computer Network, High-Level programming, and such.. I am more of a RISC person to be frankly honest Big Grin
I agree with Wryt here. The more we move towards RISC, the more we'll eventually be able to do through major trial-and-error. Sorry Tongue