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Original Transputer Instruction Set

I've recently written a brand-new instruction set for a new project of mine. It's an 8-bit MISC which is derived from the Transputer instruction set. It is a highly simplified version without multithreading. However, it does still retain the original stack-based architecture. I'll attempt to explain it here.

Each word of the instruction is comprised of a 4-bit opcode and 4-bit operand, making each word 8 bits in total. Although the operand is only 4 bits wide, it can be expanded to 8 bits using the PFIX and NFIX operations. This allows processing of 8-bit data and addresses.

There is a capability for 256 bytes of data memory and 256 bytes of program memory. In most cases, you'd want these to be separate memory spaces (Harvard architecture).

Request: I want feedback. Let it flow.

Let it flow, let it flow! This instruction set is pretty dooope!

Feedback, it's a stack machine... which is better then accumulator so I'm happy
I like it so far, what kinda clock u hoping for? Pipelined?

I'm thinking a 2-3 stage pipeline, nothing fancy. It will either be fetch-decode-execute or decode-execute. Probably no faster than 1-2 Hz execution. I'm still working out all of the technical details of the build.

Official NJSTK thread: http://forum.openredstone.org/showthread.php?tid=6040

I've updated the instruction set to better reflect the Transputer architecture. It now includes workspaces and I/O, but it does not include processes as I don't know the first thing about threading a processor.

Wait a second...
why do you have 4bit register addressing with some being SPR and most being GPR,,, when you are doing a sstack based arch.
Are your 0-11 GPRs used as addressAble stack memory? Or do you have a stack, then use registers to hold long term values?

The stack is a physically separate chunk of memory. Now that I think about it, maybe it should be in the same address space as everything else. Like I've said before, I've never built a stack architecture machine before.

UPDATE: In order to mirror the original Transputer architecture, I've merged the stack registers with the general purpose registers.

More updates: I've removed the workspace feature because that is mainly used in the process model of the original Transputer. Since I will not be supporting processes, I've removed support for workspaces.

Along with that, I've moved the additional logical instructions out of the original instruction space and into the extended instruction space, in order to reserve the process-based instructions for a possible later implementation.